Lines Matching +full:0 +full:x81000000
57 #size-cells = <0>;
60 cpu@0 {
63 reg = <0>;
83 bus-range = <0x00 0xff>;
86 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
87 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
88 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
89 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
90 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
91 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
92 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
93 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
94 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
95 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>;
98 pcie@1,0 {
100 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
101 reg = <0x0800 0 0 0 0>;
105 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
106 0x81000000 0 0 0x81000000 0x1 0 1 0>;
107 interrupt-map-mask = <0 0 0 0>;
108 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
109 marvell,pcie-port = <0>;
110 marvell,pcie-lane = <0>;
116 pcie@2,0 {
118 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
119 reg = <0x1000 0 0 0 0>;
123 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
124 0x81000000 0 0 0x81000000 0x2 0 1 0>;
125 interrupt-map-mask = <0 0 0 0>;
126 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
128 marvell,pcie-lane = <0>;
134 pcie@3,0 {
136 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
137 reg = <0x1800 0 0 0 0>;
141 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
142 0x81000000 0 0 0x81000000 0x3 0 1 0>;
143 interrupt-map-mask = <0 0 0 0>;
144 interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
146 marvell,pcie-lane = <0>;