Lines Matching +full:0 +full:x2000
42 #size-cells = <0>;
43 cpu@0 {
46 reg = <0>;
104 ranges = <0 0x44c00000 0x280000>;
108 reg = <0x200000 0x4000>;
112 #size-cells = <0>;
121 reg = <0x210000 0x2000>;
124 ranges = <0 0x210000 0x2000>;
128 reg = <0x800 0x238>;
130 #size-cells = <0>;
132 pinctrl-single,function-mask = <0x7f>;
135 scm_conf: scm_conf@0 {
137 reg = <0x0 0x800>;
143 #size-cells = <0>;
156 reg = <0x48200000 0x1000>;
162 reg = <0x49000000 0x10000>,
163 <0x44e10f90 0x40>;
175 reg = <0x44e07000 0x1000>;
186 reg = <0x4804c000 0x1000>;
197 reg = <0x481ac000 0x1000>;
208 reg = <0x481ae000 0x1000>;
216 reg = <0x44e09000 0x2000>;
228 reg = <0x48022000 0x2000>;
240 reg = <0x48024000 0x2000>;
252 reg = <0x481a6000 0x2000>;
262 reg = <0x481a8000 0x2000>;
272 reg = <0x481aa000 0x2000>;
281 #size-cells = <0>;
283 reg = <0x44e0b000 0x1000>;
291 #size-cells = <0>;
293 reg = <0x4802a000 0x1000>;
301 #size-cells = <0>;
303 reg = <0x4819c000 0x1000>;
318 reg = <0x48060000 0x1000>;
330 reg = <0x481d8000 0x1000>;
339 reg = <0x47810000 0x1000>;
345 reg = <0x480ca000 0x1000>;
353 reg = <0x44e35000 0x1000>;
360 reg = <0x481cc000 0x2000>;
363 syscon-raminit = <&scm_conf 0x644 0>;
371 reg = <0x481d0000 0x2000>;
374 syscon-raminit = <&scm_conf 0x644 1>;
381 reg = <0x480C8000 0x200>;
388 ti,mbox-tx = <0 0 0>;
389 ti,mbox-rx = <0 0 3>;
395 reg = <0x44e31000 0x400>;
403 reg = <0x48040000 0x400>;
410 reg = <0x48042000 0x400>;
417 reg = <0x48044000 0x400>;
425 reg = <0x48046000 0x400>;
433 reg = <0x48048000 0x400>;
441 reg = <0x4804a000 0x400>;
449 reg = <0x44e3e000 0x1000>;
458 #size-cells = <0>;
459 reg = <0x48030000 0x400>;
474 #size-cells = <0>;
475 reg = <0x481a0000 0x400>;
489 reg = <0x47400000 0x1000>;
498 reg = <0x44e10620 0x10
499 0x44e10648 0x4>;
506 reg = <0x47401300 0x100>;
515 reg = <0x47401400 0x400
516 0x47401000 0x200>;
528 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
529 &cppi41dma 2 0 &cppi41dma 3 0
530 &cppi41dma 4 0 &cppi41dma 5 0
531 &cppi41dma 6 0 &cppi41dma 7 0
532 &cppi41dma 8 0 &cppi41dma 9 0
533 &cppi41dma 10 0 &cppi41dma 11 0
534 &cppi41dma 12 0 &cppi41dma 13 0
535 &cppi41dma 14 0 &cppi41dma 0 1
554 reg = <0x47401b00 0x100>;
563 reg = <0x47401c00 0x400
564 0x47401800 0x200>;
575 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
576 &cppi41dma 17 0 &cppi41dma 18 0
577 &cppi41dma 19 0 &cppi41dma 20 0
578 &cppi41dma 21 0 &cppi41dma 22 0
579 &cppi41dma 23 0 &cppi41dma 24 0
580 &cppi41dma 25 0 &cppi41dma 26 0
581 &cppi41dma 27 0 &cppi41dma 28 0
582 &cppi41dma 29 0 &cppi41dma 15 1
601 reg = <0x47400000 0x1000
602 0x47402000 0x1000
603 0x47403000 0x1000
604 0x47404000 0x4000>;
617 reg = <0x48300000 0x10>;
622 ranges = <0x48300100 0x48300100 0x80 /* ECAP */
623 0x48300180 0x48300180 0x80 /* EQEP */
624 0x48300200 0x48300200 0x80>; /* EHRPWM */
629 reg = <0x48300100 0x80>;
639 reg = <0x48300200 0x80>;
647 reg = <0x48302000 0x10>;
652 ranges = <0x48302100 0x48302100 0x80 /* ECAP */
653 0x48302180 0x48302180 0x80 /* EQEP */
654 0x48302200 0x48302200 0x80>; /* EHRPWM */
659 reg = <0x48302100 0x80>;
669 reg = <0x48302200 0x80>;
677 reg = <0x48304000 0x10>;
682 ranges = <0x48304100 0x48304100 0x80 /* ECAP */
683 0x48304180 0x48304180 0x80 /* EQEP */
684 0x48304200 0x48304200 0x80>; /* EHRPWM */
689 reg = <0x48304100 0x80>;
699 reg = <0x48304200 0x80>;
712 bd_ram_size = <0x2000>;
713 no_bd_ram = <0>;
715 mac_control = <0x20>;
717 active_slave = <0>;
718 cpts_clock_mult = <0x80000000>;
720 reg = <0x4a100000 0x800
721 0x4a101200 0x100>;
738 #size-cells = <0>;
741 reg = <0x4a101000 0x100>;
757 reg= <0x44e10650 0x4>;
764 reg = <0x40300000 0x10000>; /* 64k */
769 reg = <0x44d00000 0x4000 /* M3 UMEM */
770 0x44d80000 0x2000>; /* M3 DMEM */
777 reg = <0x48080000 0x2000>;
785 reg = <0x4830e000 0x1000>;
793 reg = <0x44e0d000 0x1000>;
811 reg = <0x50000000 0x2000>;
823 reg = <0x53100000 0x200>;
832 reg = <0x53500000 0xa0>;
842 reg = <0x48038000 0x2000>,
843 <0x46000000 0x400000>;
856 reg = <0x4803C000 0x2000>,
857 <0x46400000 0x400000>;
870 reg = <0x48310000 0x2000>;