Lines Matching +full:0 +full:x0001006a
23 cpu@0 {
30 reg = <0x80000000 0x10000000>; /* 256 MB */
33 vbat: fixedregulator@0 {
54 gpio = <&gpio1 16 0>;
61 matrix_keypad: matrix_keypad@0 {
73 linux,keymap = <0x0000008b /* MENU */
74 0x0100009e /* BACK */
75 0x02000069 /* LEFT */
76 0x0001006a /* RIGHT */
77 0x0101001c /* ENTER */
78 0x0201006c>; /* DOWN */
81 gpio_keys: volume_keys@0 {
84 #size-cells = <0>;
104 pwms = <&ecap0 0 50000 0>;
105 brightness-levels = <0 51 53 56 62 75 101 152 255>;
113 pinctrl-0 = <&lcd_pins_s0>;
116 ac-bias-intrpt = <0>;
119 fdd = <0x80>;
120 sync-edge = <0>;
122 raster-order = <0>;
123 fifo-th = <0>;
159 pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
163 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
164 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */
165 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */
166 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */
167 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */
173 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */
174 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */
180 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
181 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
187 0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */
188 0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */
194 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
195 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
201 0x178 (PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */
202 0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
203 0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
204 0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
210 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
216 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
217 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
218 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
219 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
220 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
221 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
222 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
223 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
224 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
225 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
226 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
227 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
228 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
229 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
230 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
236 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
243 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
244 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
245 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
246 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
247 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
248 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
249 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
250 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
251 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
252 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
253 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
254 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
261 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
262 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
263 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
264 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
265 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
266 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
267 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
268 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
269 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
270 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
271 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
272 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
279 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
280 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
287 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
288 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
294 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
300 0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */
301 0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */
302 0x4C (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */
303 0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */
304 0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */
305 0x8C (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */
311 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 */
312 0x19C (PIN_INPUT | MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */
313 0x1AC (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */
319 0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */
320 0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */
321 0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */
322 0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */
323 0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */
324 0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */
325 0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */
326 0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */
327 0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
328 0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
329 0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
330 0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
331 0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
332 0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
333 0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
334 0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
335 0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
336 0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
337 0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
338 0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
339 0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
340 0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
341 0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
342 0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
343 0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
344 0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
345 0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
346 0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
352 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
353 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
354 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
355 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
361 0x168 (PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
362 0x16c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
369 pinctrl-0 = <&uart0_pins>;
376 pinctrl-0 = <&uart1_pins>;
383 pinctrl-0 = <&i2c0_pins>;
389 reg = <0x2d>;
424 pinctrl-0 = <&i2c1_pins>;
431 reg = <0x18>;
459 reg = <0x39>;
464 reg = <0x48>;
469 reg = <0x1b>;
494 pinctrl-0 = <&ecap0_pins>;
501 pinctrl-0 = <&nandflash_pins_s0>;
502 ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
503 nand@0,0 {
504 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
509 gpmc,sync-clk-ps = <0>;
510 gpmc,cs-on-ns = <0>;
516 gpmc,we-on-ns = <0>;
518 gpmc,oe-on-ns = <0>;
525 gpmc,bus-turnaround-ns = <0>;
526 gpmc,cycle2cycle-delay-ns = <0>;
527 gpmc,clk-activation-ns = <0>;
528 gpmc,wait-monitoring-ns = <0>;
530 gpmc,wr-data-mux-bus-ns = <0>;
537 partition@0 {
539 reg = <0x00000000 0x000020000>;
543 reg = <0x00020000 0x00020000>;
547 reg = <0x00040000 0x00020000>;
551 reg = <0x00060000 0x00020000>;
555 reg = <0x00080000 0x00040000>;
559 reg = <0x000C0000 0x00100000>;
563 reg = <0x001C0000 0x00020000>;
567 reg = <0x001E0000 0x00020000>;
571 reg = <0x00200000 0x00800000>;
575 reg = <0x00A00000 0x0F600000>;
584 pinctrl-0 = <&am335x_evm_audio_pins>;
588 op-mode = <0>; /* MCASP_IIS_MODE */
591 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
592 0 0 1 2
609 vrtc_reg: regulator@0 {
677 pinctrl-0 = <&cpsw_default>;
684 pinctrl-0 = <&davinci_mdio_default>;
690 phy_id = <&davinci_mdio>, <0>;
705 ti,wire-config = <0x00 0x11 0x22 0x33>;
706 ti,charge-delay = <0x400>;
719 pinctrl-0 = <&mmc1_pins>;
733 pinctrl-0 = <&mmc3_pins &wlan_pins>;
740 #size-cells = <0>;
741 wlcore: wlcore@0 {
765 pinctrl-0 = <&dcan1_pins_default>;