Lines Matching +full:0 +full:x148
11 cpu@0 {
23 reg = <0x80000000 0x10000000>; /* 256 MB */
28 pinctrl-0 = <&user_leds_s0>;
61 vmmcsd_fixed: fixedregulator@0 {
71 pinctrl-0 = <&clkout2_pin>;
75 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
76 0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */
77 0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */
78 0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */
84 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
85 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
91 0x178 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.i2c2_sda */
92 0x17c (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.i2c2_scl */
98 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
99 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
105 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
112 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */
113 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
114 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
115 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
116 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
117 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
118 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
119 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */
120 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
121 0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
122 0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
123 0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
124 0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
131 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
132 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
133 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
134 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
135 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
136 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
137 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
138 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
139 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
140 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
141 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
142 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
143 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
150 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
151 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
158 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
159 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
165 0x160 (PIN_INPUT | MUX_MODE7) /* GPIO0_6 */
171 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
172 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
173 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
174 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
175 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
176 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
177 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
178 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
179 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
180 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
187 pinctrl-0 = <&uart0_pins>;
224 pinctrl-0 = <&i2c0_pins>;
230 reg = <0x24>;
235 reg = <0x50>;
239 baseboard_data: baseboard_data@0 {
240 reg = <0 0x100>;
247 pinctrl-0 = <&i2c2_pins>;
254 reg = <0x54>;
257 cape0_data: cape_data@0 {
258 reg = <0 0x100>;
264 reg = <0x55>;
267 cape1_data: cape_data@0 {
268 reg = <0 0x100>;
274 reg = <0x56>;
277 cape2_data: cape_data@0 {
278 reg = <0 0x100>;
284 reg = <0x57>;
287 cape3_data: cape_data@0 {
288 reg = <0 0x100>;
317 dcdc1_reg: regulator@0 {
363 phy_id = <&davinci_mdio>, <0>;
374 pinctrl-0 = <&cpsw_default>;
381 pinctrl-0 = <&davinci_mdio_default>;
388 bus-width = <0x4>;
390 pinctrl-0 = <&mmc1_pins>;