Lines Matching refs:x0
71 adr x0, _start /* x0 <- Runtime value of _start */
73 sub x9, x0, x1 /* x9 <- Run-vs-link offset */
77 ldp x0, x1, [x2], #16 /* (x0, x1) <- (Link location, fixup) */
82 add x0, x0, x9
84 str x4, [x0]
98 adr x0, vectors
100 3: msr vbar_el3, x0
101 mrs x0, scr_el3
102 orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */
103 msr scr_el3, x0
106 ldr x0, =COUNTER_FREQUENCY
107 msr cntfrq_el0, x0 /* Initialize CNTFRQ */
110 2: msr vbar_el2, x0
111 mov x0, #0x33ff
112 msr cptr_el2, x0 /* Enable FP/SIMD */
114 1: msr vbar_el1, x0
115 mov x0, #3 << 20
116 msr cpacr_el1, x0 /* Enable FP/SIMD */
129 3: mrs x0, sctlr_el3
130 orr x0, x0, x1
131 msr sctlr_el3, x0
136 2: mrs x0, sctlr_el2
137 orr x0, x0, x1
138 msr sctlr_el2, x0
140 mrs x0, hcr_el2
141 orr x0, x0, #HCR_EL2_TGE
142 orr x0, x0, #HCR_EL2_AMO
144 orr x0, x0, #HCR_EL2_IMO
146 msr hcr_el2, x0
149 1: mrs x0, sctlr_el1
150 orr x0, x0, x1
151 msr sctlr_el1, x0
164 mrs x0, S3_1_c15_c2_1 /* cpuectlr_el1 */
165 orr x0, x0, #0x40
166 msr S3_1_c15_c2_1, x0
184 branch_if_master x0, x1, master_cpu
188 branch_if_master x0, x1, master_cpu
196 ldr x0, [x1]
197 cbz x0, slave_cpu
198 br x0 /* branch to the given address */
202 mrs x0, mpidr_el1
203 and x0, x0, #0xfff
204 cmp x0, #0
208 cmp x0, #(SMP_CPU1)
214 cmp x0, #(SMP_CPU2)
220 cmp x0, #(SMP_CPU3)
244 mrs x0, sctlr_el3
247 mrs x0, sctlr_el2
250 mrs x0, sctlr_el1
254 and x0, x0, x1
258 msr sctlr_el3, x0
261 msr sctlr_el2, x0
264 msr sctlr_el1, x0
281 branch_if_a57_core x0, apply_a57_core_errata
289 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
291 orr x0, x0, #1 << 49
293 orr x0, x0, #3 << 25
295 orr x0, x0, #3 << 27
296 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
300 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
302 orr x0, x0, #1 << 59
303 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
307 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
311 orr x0, x0, #1 << 38
312 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
316 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
321 orr x0, x0, #1 << 4
322 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
326 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
328 and x0, x0, #0xE
329 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
340 branch_if_slave x0, 1f
341 ldr x0, =GICD_BASE
345 ldr x0, =GICR_BASE
348 ldr x0, =GICD_BASE
355 branch_if_master x0, x1, 2f
364 ldr x0, =GICC_BASE
395 ldr x0, =GICD_BASE
405 adr x0, vectors
407 3: msr vbar_el3, x0
409 2: msr vbar_el2, x0
411 1: msr vbar_el1, x0