Lines Matching refs:msr
100 3: msr vbar_el3, x0
103 msr scr_el3, x0
104 msr cptr_el3, xzr /* Enable FP/SIMD */
107 msr cntfrq_el0, x0 /* Initialize CNTFRQ */
110 2: msr vbar_el2, x0
112 msr cptr_el2, x0 /* Enable FP/SIMD */
114 1: msr vbar_el1, x0
116 msr cpacr_el1, x0 /* Enable FP/SIMD */
131 msr sctlr_el3, x0
133 msr daifclr, #4 /* Enable SError. SCR_EL3.EA=1 was already set in start.S */
138 msr sctlr_el2, x0
146 msr hcr_el2, x0
147 msr daifclr, #4
151 msr sctlr_el1, x0
152 msr daifclr, #4
166 msr S3_1_c15_c2_1, x0
258 msr sctlr_el3, x0
261 msr sctlr_el2, x0
264 msr sctlr_el1, x0
296 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
303 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
312 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
322 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
329 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
407 3: msr vbar_el3, x0
409 2: msr vbar_el2, x0
411 1: msr vbar_el1, x0