Lines Matching refs:gd
75 gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE; in early_mmu_setup()
76 gd->arch.tlb_fillptr = gd->arch.tlb_addr; in early_mmu_setup()
77 gd->arch.tlb_size = EARLY_PGTABLE_SIZE; in early_mmu_setup()
83 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, in early_mmu_setup()
145 u64 tlb_addr_save = gd->arch.tlb_addr; in final_mmu_setup()
163 final_map[index].virt = gd->bd->bi_dram[0].start; in final_mmu_setup()
164 final_map[index].phys = gd->bd->bi_dram[0].start; in final_mmu_setup()
165 final_map[index].size = gd->bd->bi_dram[0].size; in final_mmu_setup()
170 final_map[index].virt = gd->bd->bi_dram[1].start; in final_mmu_setup()
171 final_map[index].phys = gd->bd->bi_dram[1].start; in final_mmu_setup()
172 final_map[index].size = gd->bd->bi_dram[1].size; in final_mmu_setup()
181 final_map[index].virt = gd->bd->bi_dram[2].start; in final_mmu_setup()
182 final_map[index].phys = gd->bd->bi_dram[2].start; in final_mmu_setup()
183 final_map[index].size = gd->bd->bi_dram[2].size; in final_mmu_setup()
195 if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) { in final_mmu_setup()
203 gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff; in final_mmu_setup()
204 final_map[index].virt = gd->arch.secure_ram & ~0x3; in final_mmu_setup()
208 gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED; in final_mmu_setup()
209 tlb_addr_save = gd->arch.tlb_addr; in final_mmu_setup()
212 tlb_addr_save = gd->arch.tlb_allocated; in final_mmu_setup()
213 gd->arch.tlb_addr = tlb_addr_save; in final_mmu_setup()
219 gd->arch.tlb_fillptr = tlb_addr_save; in final_mmu_setup()
225 gd->arch.tlb_addr = gd->arch.tlb_fillptr; in final_mmu_setup()
226 gd->arch.tlb_emerg = gd->arch.tlb_addr; in final_mmu_setup()
228 gd->arch.tlb_addr = tlb_addr_save; in final_mmu_setup()
235 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL), in final_mmu_setup()
644 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { in get_effective_memsize()
646 rem = gd->ram_size - ea_size; in get_effective_memsize()
648 ea_size = gd->ram_size; in get_effective_memsize()
689 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; in dram_init_banksize()
690 if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { in dram_init_banksize()
691 gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; in dram_init_banksize()
692 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; in dram_init_banksize()
693 gd->bd->bi_dram[1].size = gd->ram_size - in dram_init_banksize()
696 if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) { in dram_init_banksize()
697 gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE; in dram_init_banksize()
698 gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size - in dram_init_banksize()
700 gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE; in dram_init_banksize()
704 gd->bd->bi_dram[0].size = gd->ram_size; in dram_init_banksize()
708 if (gd->bd->bi_dram[2].size >= CONFIG_SYS_MEM_RESERVE_SECURE) { in dram_init_banksize()
709 gd->bd->bi_dram[2].size -= CONFIG_SYS_MEM_RESERVE_SECURE; in dram_init_banksize()
710 gd->arch.secure_ram = gd->bd->bi_dram[2].start + in dram_init_banksize()
711 gd->bd->bi_dram[2].size; in dram_init_banksize()
712 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; in dram_init_banksize()
713 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; in dram_init_banksize()
717 if (gd->bd->bi_dram[1].size >= CONFIG_SYS_MEM_RESERVE_SECURE) { in dram_init_banksize()
718 gd->bd->bi_dram[1].size -= in dram_init_banksize()
720 gd->arch.secure_ram = gd->bd->bi_dram[1].start + in dram_init_banksize()
721 gd->bd->bi_dram[1].size; in dram_init_banksize()
722 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; in dram_init_banksize()
723 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; in dram_init_banksize()
724 } else if (gd->bd->bi_dram[0].size > in dram_init_banksize()
726 gd->bd->bi_dram[0].size -= in dram_init_banksize()
728 gd->arch.secure_ram = gd->bd->bi_dram[0].start + in dram_init_banksize()
729 gd->bd->bi_dram[0].size; in dram_init_banksize()
730 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; in dram_init_banksize()
731 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; in dram_init_banksize()
739 if (gd->bd->bi_dram[2].size >= in dram_init_banksize()
740 board_reserve_ram_top(gd->bd->bi_dram[2].size)) { in dram_init_banksize()
741 gd->arch.resv_ram = gd->bd->bi_dram[2].start + in dram_init_banksize()
742 gd->bd->bi_dram[2].size - in dram_init_banksize()
743 board_reserve_ram_top(gd->bd->bi_dram[2].size); in dram_init_banksize()
747 if (gd->bd->bi_dram[1].size >= in dram_init_banksize()
748 board_reserve_ram_top(gd->bd->bi_dram[1].size)) { in dram_init_banksize()
749 gd->arch.resv_ram = gd->bd->bi_dram[1].start + in dram_init_banksize()
750 gd->bd->bi_dram[1].size - in dram_init_banksize()
751 board_reserve_ram_top(gd->bd->bi_dram[1].size); in dram_init_banksize()
752 } else if (gd->bd->bi_dram[0].size > in dram_init_banksize()
753 board_reserve_ram_top(gd->bd->bi_dram[0].size)) { in dram_init_banksize()
754 gd->arch.resv_ram = gd->bd->bi_dram[0].start + in dram_init_banksize()
755 gd->bd->bi_dram[0].size - in dram_init_banksize()
756 board_reserve_ram_top(gd->bd->bi_dram[0].size); in dram_init_banksize()
778 gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; in dram_init_banksize()
779 gd->bd->bi_dram[2].size = dp_ddr_size; in dram_init_banksize()
806 ram_start = gd->bd->bi_dram[i].start; in efi_add_known_memory()
807 ram_size = gd->bd->bi_dram[i].size; in efi_add_known_memory()
809 if (gd->arch.resv_ram >= ram_start && in efi_add_known_memory()
810 gd->arch.resv_ram < ram_start + ram_size) in efi_add_known_memory()
811 ram_size = gd->arch.resv_ram - ram_start; in efi_add_known_memory()
831 if (!gd->arch.tlb_addr) in update_early_mmu_table()
834 if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) { in update_early_mmu_table()
837 gd->ram_size, in update_early_mmu_table()
854 if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE > in update_early_mmu_table()
865 gd->ram_size - in update_early_mmu_table()
877 gd->ram_size - in update_early_mmu_table()