cpu/armv8/cache.S

7  * SPDX-License-Identifier:	GPL-2.0+
10 #include <asm-offsets.h>
19  * flush or invalidate one level cache.
21  * x0: cache level
28 	msr	csselr_el1, x12		/* select cache level */
31 	and	x2, x6, #7		/* x2 <- log2(cache line size)-4 */
32 	add	x2, x2, #4		/* x2 <- log2(cache line size) */
34 	and	x3, x3, x6, lsr #3	/* x3 <- max number of #ways */
37 	and	x4, x4, x6, lsr #13	/* x4 <- max number of #sets */
38 	/* x12 <- cache level << 1 */
39 	/* x2 <- line length offset */
40 	/* x3 <- number of cache ways - 1 */
41 	/* x4 <- number of cache sets - 1 */
42 	/* x5 <- bit position of #ways */
45 	mov	x6, x3			/* x6 <- working copy of #ways */
69  * flush or invalidate all data cache by SET/WAY.
77 	and	x11, x11, #0x7		/* x11 <- loc */
80 	mov	x0, #0			/* start flush at cache level 0 */
81 	/* x0  <- cache level */
82 	/* x10 <- clidr_el1 */
83 	/* x11 <- loc */
84 	/* x15 <- return address */
88 	add	x12, x12, x0		/* x0 <- tripled cache level */
90 	and	x12, x12, #7		/* x12 <- cache type */
92 	b.lt	skip			/* skip if no cache or icache */
95 	add	x0, x0, #1		/* increment cache level */
127  * clean & invalidate data cache in the range
139 	lsl	x2, x2, x3		/* cache line size */
141 	/* x2 <- minimal cache line size in cache system */
144 1:	dc	civac, x0	/* clean & invalidate data or unified cache */
156  * invalidate data cache in the range
166 	lsl	x2, x2, x3		/* cache line size */
168 	/* x2 <- minimal cache line size in cache system */
171 1:	dc	ivac, x0	/* invalidate data or unified cache */