Lines Matching +full:psci +full:- +full:0

4         bool "Enable multiple CPUs to enter into U-Boot"
10 	  CPUECTLR_EL1.SMPEN bit before U-Boot.
25 	bool "Support spin-table enable method"
28 	  Say Y here to support "spin-table" enable method for booting Linux.
31 	    - Specify enable-method = "spin-table" in each CPU node in the
33 	    - Bring secondary CPUs into U-Boot proper in a board specific
38 	  U-Boot automatically does:
39 	    - Set "cpu-release-addr" property of each CPU node
41 	    - Reserve the code for the spin-table and the release address
54 	    - Address of secure firmware.
55 	    - Address to hold the return address from secure firmware.
56 	    - Secure firmware FIT image related information.
58 	    - The target exception level that secure monitor firmware will
69 	bool "PSCI implementation in secure monitor firmware"
72 	  This config enables the ARMv8 PSCI implementation in secure monitor
73 	  firmware. This is a private PSCI implementation and different from
74 	  those implemented under the common ARMv8 PSCI framework.
86 	bool "Use PSCI for reset and shutdown"
97 	  Most armv8 systems have PSCI support enabled in EL3, either through
103 	  Select Y here to make use of PSCI calls for system reset
106 	bool "Enable PSCI support" if EXPERT
109 	  PSCI is Power State Coordination Interface defined by ARM.
110 	  The PSCI in U-boot provides a general framework and each platform
111 	  can implement their own specific PSCI functions.
112 	  Say Y here to enable PSCI support on ARMv8 platform.
115 	int "Maximum supported CPUs for PSCI"
119 	  The maximum number of CPUs supported in the PSCI firmware.
126 	default 0
130 	  A value 0 or no definition of it works for single cluster system.
131 	  System with multi-cluster should difine their own exact value.
136 	hex "Secure address for PSCI image"
139 	  Address for placing the PSCI text, data and stack sections.
140 	  If not defined, the PSCI sections are placed together with the u-boot
141 	  but platform can choose to place PSCI code image separately in other
142 	  places such as some secure RAM built-in SOC etc.
152 	bool "SHA-1 digest algorithm (ARMv8 Crypto Extensions)"
156 	bool "SHA-256 digest algorithm (ARMv8 Crypto Extensions)"