Lines Matching +full:non +full:- +full:secure

5  * Routines to transition ARMv7 processors from secure into non-secure state
6  * and from non-secure SVC into HYP mode
9  * SPDX-License-Identifier:	GPL-2.0+
16 #include <asm/secure.h>
42 		return -1;  in get_gicd_base_address()
56 	size_t sz = __secure_end - __secure_start;  in relocate_secure_section()
79 	if (gic_dist_addr == -1)  in smp_kick_all_cpus()
99 		return -1;  in armv7_init_nonsec()
103 	 * according to the spec one should not tinker with it in secure state  in armv7_init_nonsec()
104 	 * in SVC mode. Do not try to read it once in non-secure state,  in armv7_init_nonsec()
109 	if (gic_dist_addr == -1)  in armv7_init_nonsec()
110 		return -1;  in armv7_init_nonsec()
120 	 * from non-secure state. The first 32 interrupts are private per  in armv7_init_nonsec()
124 		writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);  in armv7_init_nonsec()
129 	 * Relocate secure section before any cpu runs in secure ram.  in armv7_init_nonsec()
130 	 * smp_kick_all_cpus may enable other cores and runs into secure  in armv7_init_nonsec()
131 	 * ram, so need to relocate secure section before enabling other  in armv7_init_nonsec()
137 	smp_set_core_boot_addr((unsigned long)secure_ram_addr(_smp_pen), -1);  in armv7_init_nonsec()
141 	/* call the non-sec switching code on this CPU also */  in armv7_init_nonsec()