Lines Matching full:r0
49 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
50 and r0, r0, #CPUID_ARM_VIRT_MASK @ mask virtualization bits
51 cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT)
59 mrs r0, cpsr
60 and r1, r0, #0x1f @ mask mode bits
62 bicne r0, r0, #0x1f @ clear all mode bits
63 orrne r0, r0, #0x13 @ set SVC mode
64 orr r0, r0, #0xc0 @ disable FIQ and IRQ
65 msr cpsr,r0
68 mrc p15, 0, r0, c1, c0, 1
69 orr r0, r0, #(1 << 6) @ Enable ACTLR.SMP bit
70 mcr p15, 0, r0, c1, c0, 1
79 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register
80 bic r0, #CR_V @ V = 0
81 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTLR Register
84 ldr r0, =_start
85 mcr p15, 0, r0, c12, c0, 0 @Set VBAR
89 mrs r0, cpsr
90 bic r0, r0, #0x100 @ CPSR.A bit
91 msr cpsr_x,r0
110 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
111 mcr p15, 0, r0, c7, c10, 4 @ DSB
112 mcr p15, 0, r0, c7, c5, 4 @ ISB
123 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
154 mov r0, #0 @ set up for MCR
155 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
156 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
157 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
158 mcr p15, 0, r0, c7, c10, 4 @ DSB
159 mcr p15, 0, r0, c7, c5, 4 @ ISB
164 mrc p15, 0, r0, c1, c0, 0
165 bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
166 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
168 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
170 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
172 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
174 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
176 mcr p15, 0, r0, c1, c0, 0
179 mrc p15, 0, r0, c1, c0, 0 @ read system control register
180 orr r0, r0, #1 << 11 @ set bit #11
181 mcr p15, 0, r0, c1, c0, 0 @ write system control register
185 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
186 orr r0, r0, #1 << 4 @ set bit #4
187 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
191 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
192 orr r0, r0, #1 << 6 @ set bit #6
193 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
197 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
198 orr r0, r0, #1 << 11 @ set bit #11
199 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
202 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
203 orr r0, r0, #1 << 21 @ set bit #21
204 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
208 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
209 orr r0, r0, #1 << 22 @ set bit #22
210 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
227 mrc p15, 1, r0, c15, c0, 0 @ read l2 aux ctrl reg
228 orr r0, r0, #1 << 7 @ Enable hazard-detect timeout
241 mrc p15, 0, r0, c0, c0, 6 @ pick up REVIDR reg
242 and r0, r0, #1 << 3 @ check REVIDR[3]
243 cmp r0, #1 << 3
246 mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register
247 orr r0, r0, #3 << 27 @ Disables streaming. All write-allocate
249 orr r0, r0, #3 << 25 @ Disables streaming. All write-allocate
261 mrc p15, 0, r0, c1, c0, 1 @ Read ACR
262 orr r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits
274 mrc p15, 0, r0, c1, c0, 1 @ Read ACR
275 orr r0, r0, #(0x1 << 6) @ Set IBE bit
287 mrc p15, 0, r0, c1, c0, 1 @ Read ACR
288 orr r0, r0, #(0x1 << 5) @ Set L1NEON bit
300 mrc p15, 1, r0, c9, c0, 2 @ Read L2ACR
301 orr r0, r0, #(0x1 << 27) @ L2 PLD data forwarding disable
310 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
311 orr r0, r0, #1 << 24 @ set bit #24
312 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
316 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
317 orr r0, r0, #1 << 12 @ set bit #12
318 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
332 mrc p15, 0, r0, c1, c1, 0
333 orr r0, r0, #(1 << 0)
334 mcr p15, 0, r0, c1, c1, 0
338 mov r0, #0
339 mcrr p15, 4, r0, r0, c14 @ CNTVOFF
342 mrc p15, 0, r0, c1, c1, 0
343 bic r0, r0, #(1 << 0)
344 mcr p15, 0, r0, c1, c1, 0