Lines Matching +full:0 +full:xf01

15 #define RCPM_TWAITSR		0x04C
17 #define SCFG_CORE0_SFT_RST      0x130
18 #define SCFG_CORESRENCR         0x204
20 #define DCFG_CCSR_RSTCR			0x0B0
21 #define DCFG_CCSR_RSTCR_RESET_REQ	0x2
22 #define DCFG_CCSR_BRR			0x0E4
23 #define DCFG_CCSR_SCRATCHRW1		0x200
25 #define PSCI_FN_PSCI_VERSION_FEATURE_MASK	0x0
26 #define PSCI_FN_CPU_SUSPEND_FEATURE_MASK	0x0
27 #define PSCI_FN_CPU_OFF_FEATURE_MASK		0x0
28 #define PSCI_FN_CPU_ON_FEATURE_MASK		0x0
29 #define PSCI_FN_AFFINITY_INFO_FEATURE_MASK	0x0
30 #define PSCI_FN_SYSTEM_OFF_FEATURE_MASK		0x0
31 #define PSCI_FN_SYSTEM_RESET_FEATURE_MASK	0x0
32 #define PSCI_FN_SYSTEM_SUSPEND_FEATURE_MASK	0x0
45 	movw	r0, #0
67 	.word	0
74 	cmp	r3, #0
90 	and	r4, r1, #0xff
94 	tst	r1, #0xff000000
98 	tst	r1, #0xff0000
101 	@ Affinity level 1 - Processors: should be in 0xf00 format.
103 	teq	r1, #0xf
106 	@ Affinity level 0 - CPU: only 0, 1 are valid in LS1021xa.
121 	@ r1 = 0xf01
132 	movw	r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
144 	movw	r0, #(CONFIG_SYS_FSL_SCFG_ADDR & 0xffff)
148 	movw	r5, #0
154 	mov	r6, #0x4
159 	movw	r5, #0
168 	mov	r5, #0
210 	cmp	r2, #0
219 	movw	r4, #(CONFIG_SYS_FSL_RCPM_ADDR & 0xffff)
239 	movw	r1, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)