21 #define DCSR_RCPM2_BLOCK_OFFSET	0x223000
22 #define DCSR_RCPM2_CPMFSMCR0	0x400
23 #define DCSR_RCPM2_CPMFSMSR0	0x404
24 #define DCSR_RCPM2_CPMFSMCR1	0x414
25 #define DCSR_RCPM2_CPMFSMSR1	0x418
26 #define CPMFSMSR_FSM_STATE_MASK	0x7f
34  * and bit[0] indicates whether the descriptor is valid.
36 #define PMD_TYPE_TABLE		0x3
37 #define PMD_TYPE_SECT		0x1
39 /* AttrIndx[2:0] */
50 #define TTBCR_T0SZ(x)		((x) << 0)
52 #define TTBCR_USING_TTBR0	(TTBCR_T0SZ(0) | TTBCR_T1SZ(0))
53 #define TTBCR_IRGN0_NC		(0 << 8)
58 #define TTBCR_ORGN0_NC		(0 << 10)
63 #define TTBCR_SHARED_NON	(0 << 12)
66 #define TTBCR_EPD0		(0 << 7)
76  * n = AttrIndx[2:0]
91 #define MT_MAIR0		0xeeaa4400
92 #define MT_MAIR1		0xff000004
93 #define MT_STRONLY_ORDER	0
104 	page_table[2 * index + 1] = 0;  in set_pgtable()
115 	page_table[2 * index] = value & 0xFFFFFFFF;  in set_pgsection()
116 	page_table[2 * index + 1] = (value >> 32) & 0xFFFFFFFF;  in set_pgsection()
128  *  -------  <---- 0GB
131  * |-------| <---- 0x24000000
132  * |///////|  ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000
133  * |-------| <---- 0x300000000
135  * |-------| <---- 0x34000000
136  * |///////|  ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000
137  * |-------| <---- 0x40000000
139  * |-------| <---- 0x80000000 DDR0 space start
148 	u32 *level1_table = (u32 *)(gd->arch.tlb_addr + 0x1000);  in mmu_setup()
149 	u64 va_start = 0;  in mmu_setup()
153 	/* Level 0 Table 2-3 are used to map DDR */  in mmu_setup()
156 	/* Level 0 Table 1 is used to map device */  in mmu_setup()
158 	/* Level 0 Table 0 is used to map device including PCIe MEM */  in mmu_setup()
159 	set_pgtable(level0_table, 0, (u32)level1_table);  in mmu_setup()
162 	for (i = 0; i < 512; i++) {  in mmu_setup()
185 	asm volatile("mcr p15, 0, %0, c2, c0, 2" /* Write RT to TTBCR */  in mmu_setup()
187 	asm volatile("mcrr p15, 0, %0, %1, c2" /* TTBR 0 */  in mmu_setup()
188 			: : "r" ((u32)level0_table), "r" (0) : "memory");  in mmu_setup()
189 	asm volatile("mcr p15, 0, %0, c10, c2, 0" /* write MAIR 0 */  in mmu_setup()
191 	asm volatile("mcr p15, 0, %0, c10, c2, 1" /* write MAIR 1 */  in mmu_setup()
195 	asm volatile("mcr p15, 0, %0, c3, c0, 0"  in mmu_setup()
196 		     : : "r" (~0));  in mmu_setup()
264 	printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);  in print_cpuinfo()
278 	for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {  in print_cpuinfo()
281 		if ((i % 4) == 0)  in print_cpuinfo()
287 	return 0;  in print_cpuinfo()
304 	return 0;  in cpu_eth_init()
321 	if (state != 0) {  in arch_cpu_init()
322 		out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x80);  in arch_cpu_init()
323 		out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x0);  in arch_cpu_init()
328 	if (state != 0) {  in arch_cpu_init()
329 		out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x80);  in arch_cpu_init()
330 		out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x0);  in arch_cpu_init()
342 	return 0;  in arch_cpu_init()
351 	out_be32(&gur->scratchrw[0], addr);  in smp_set_core_boot_addr()
359 	out_be32(&gur->brrl, 0x2);  in smp_kick_all_cpus()
389 	asm("mrc p15, 0, %0, c14, c2, 1" : "=r" (ctrl));  in arch_preboot_os()
391 	asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl));  in arch_preboot_os()