33 	u32 ddr1v8, ddr2v5;  in sel_1v8()  local
40 	ddr1v8 = readl(&misc_p->ddr_1v8_compensation);  in sel_1v8()
41 	ddr1v8 &= 0x8080ffc0;  in sel_1v8()
42 	ddr1v8 |= 0x78000010;  in sel_1v8()
43 	writel(ddr1v8, &misc_p->ddr_1v8_compensation);  in sel_1v8()
52 	u32 ddr1v8, ddr2v5;  in sel_2v5()  local
54 	ddr1v8 = readl(&misc_p->ddr_1v8_compensation);  in sel_2v5()
55 	ddr1v8 &= 0x8080ffc0;  in sel_2v5()
56 	ddr1v8 |= 0x78000003;  in sel_2v5()
57 	writel(ddr1v8, &misc_p->ddr_1v8_compensation);  in sel_2v5()
75 	u32 core3v3, ddr1v8, ddr2v5;  in plat_ddr_init()  local
96 	ddr1v8 = readl(&misc_p->ddr_1v8_compensation);  in plat_ddr_init()
97 	ddr1v8 &= 0x8080ffc0;  in plat_ddr_init()
98 	ddr1v8 |= 0x78000004;  in plat_ddr_init()
99 	writel(ddr1v8, &misc_p->ddr_1v8_compensation);  in plat_ddr_init()