19 	writel(0x80000007, &misc_p->arb_icm_ml1);  in spear_late_init()
20 	writel(0x80000007, &misc_p->arb_icm_ml2);  in spear_late_init()
21 	writel(0x80000007, &misc_p->arb_icm_ml3);  in spear_late_init()
22 	writel(0x80000007, &misc_p->arb_icm_ml4);  in spear_late_init()
23 	writel(0x80000007, &misc_p->arb_icm_ml5);  in spear_late_init()
24 	writel(0x80000007, &misc_p->arb_icm_ml6);  in spear_late_init()
25 	writel(0x80000007, &misc_p->arb_icm_ml7);  in spear_late_init()
26 	writel(0x80000007, &misc_p->arb_icm_ml8);  in spear_late_init()
27 	writel(0x80000007, &misc_p->arb_icm_ml9);  in spear_late_init()
36 	ddr2v5 &= 0x8080ffc0;  in sel_1v8()
37 	ddr2v5 |= 0x78000003;  in sel_1v8()
41 	ddr1v8 &= 0x8080ffc0;  in sel_1v8()
42 	ddr1v8 |= 0x78000010;  in sel_1v8()
55 	ddr1v8 &= 0x8080ffc0;  in sel_2v5()
56 	ddr1v8 |= 0x78000003;  in sel_2v5()
60 	ddr2v5 &= 0x8080ffc0;  in sel_2v5()
61 	ddr2v5 |= 0x78000010;  in sel_2v5()
82 	ddrpad |= 0xEAAB;  in plat_ddr_init()
84 	ddrpad |= 0xEAAD;  in plat_ddr_init()
86 	ddrpad |= 0xEAAD;  in plat_ddr_init()
92 	core3v3 &= 0x8080ffe0;  in plat_ddr_init()
93 	core3v3 |= 0x78000002;  in plat_ddr_init()
97 	ddr1v8 &= 0x8080ffc0;  in plat_ddr_init()
98 	ddr1v8 |= 0x78000004;  in plat_ddr_init()
102 	ddr2v5 &= 0x8080ffc0;  in plat_ddr_init()
103 	ddr2v5 |= 0x78000004;  in plat_ddr_init()