22 #include <asm/arch/emc.h>
26 static struct emc_regs *emc = (struct emc_regs *)EMC_BASE;  variable
32 	/* Enable EMC interface and choose little endian mode */  in ddr_init()
33 	writel(1, &emc->ctrl);  in ddr_init()
34 	writel(0, &emc->config);  in ddr_init()
35 	/* Select maximum EMC Dynamic Memory Refresh Time */  in ddr_init()
36 	writel(0x7FF, &emc->refresh);  in ddr_init()
41 	writel(dram->config0, &emc->config0);  in ddr_init()
42 	writel(dram->rascas0, &emc->rascas0);  in ddr_init()
43 	writel(dram->rdconfig, &emc->read_config);  in ddr_init()
45 	writel((ck / dram->trp) & 0x0000000F, &emc->t_rp);  in ddr_init()
46 	writel((ck / dram->tras) & 0x0000000F, &emc->t_ras);  in ddr_init()
47 	writel((ck / dram->tsrex) & 0x0000007F, &emc->t_srex);  in ddr_init()
48 	writel((ck / dram->twr) & 0x0000000F, &emc->t_wr);  in ddr_init()
49 	writel((ck / dram->trc) & 0x0000001F, &emc->t_rc);  in ddr_init()
50 	writel((ck / dram->trfc) & 0x0000001F, &emc->t_rfc);  in ddr_init()
51 	writel((ck / dram->txsr) & 0x000000FF, &emc->t_xsr);  in ddr_init()
52 	writel(dram->trrd, &emc->t_rrd);  in ddr_init()
53 	writel(dram->tmrd, &emc->t_mrd);  in ddr_init()
54 	writel(dram->tcdlr, &emc->t_cdlr);  in ddr_init()
56 	writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh);  in ddr_init()
59 	writel(0x00000193, &emc->control);  in ddr_init()
62 	writel(0x00000113, &emc->control);  in ddr_init()
64 	writel((((128) >> 4) & 0x7FF), &emc->refresh);  in ddr_init()
67 	writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh);  in ddr_init()
70 	writel(0x00000093, &emc->control);  in ddr_init()
73 	writel(0x00000093, &emc->control);  in ddr_init()
76 	writel(0x00000010, &emc->control);  in ddr_init()