Lines Matching refs:write_aux_reg
55 write_aux_reg(ARC_AUX_SLC_CTRL, reg & ~DC_CTRL_INV_MODE_FLUSH); in __before_slc_op()
76 write_aux_reg(ARC_AUX_SLC_CTRL, reg | DC_CTRL_INV_MODE_FLUSH); in __after_slc_op()
95 write_aux_reg(aux_cmd, paddr); in __slc_line_loop()
110 write_aux_reg(aux, 0x1); in __slc_entire_op()
234 write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE, in cache_init()
242 write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12); in cache_init()
243 write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1); in cache_init()
244 write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1); in cache_init()
264 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) & in icache_enable()
271 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) | in icache_disable()
280 write_aux_reg(ARC_AUX_IC_IVIC, 1); in invalidate_icache_all()
306 write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) & in dcache_enable()
315 write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) | in dcache_disable()
352 write_aux_reg(aux_tag, paddr); in __cache_line_loop()
354 write_aux_reg(aux_cmd, paddr); in __cache_line_loop()
369 write_aux_reg(ARC_AUX_DC_CTRL, reg & ~DC_CTRL_INV_MODE_FLUSH); in __before_dc_op()
383 write_aux_reg(ARC_AUX_DC_CTRL, reg | DC_CTRL_INV_MODE_FLUSH); in __after_dc_op()
396 write_aux_reg(aux, 0x1); in __dc_entire_op()