Lines Matching full:accesses
32 for cachelines with highest contention - highest number of HITM accesses.
178 - cacheline percentage of all Remote/Local HITM accesses
184 - sum of all cachelines accesses
187 - sum of all load accesses
190 - sum of all store accesses
193 L1Hit - store accesses that hit L1
194 L1Miss - store accesses that missed L1
200 - count of LLC load accesses, includes LLC hits and LLC HITMs
203 - count of remote load accesses, includes remote hits and remote HITMs
206 - count of local and remote DRAM accesses
211 - % of Remote/Local HITM accesses for given offset within cacheline
214 - % of store accesses that hit/missed L1 for given offset within cacheline
220 - pid of the process responsible for the accesses
223 - tid of the process responsible for the accesses
226 - code address responsible for the accesses
229 - sum of cycles for given accesses - Remote/Local HITM and generic load
248 The 'Node' field displays nodes that accesses given cacheline
280 - overall statistics of memory accesses