Lines Matching refs:msp
117 static void set_prot_desc_tx(struct ux500_msp *msp, in set_prot_desc_tx() argument
127 if (msp->def_elem_len) { in set_prot_desc_tx()
141 writel(temp_reg, msp->registers + MSP_TCF); in set_prot_desc_tx()
144 static void set_prot_desc_rx(struct ux500_msp *msp, in set_prot_desc_rx() argument
154 if (msp->def_elem_len) { in set_prot_desc_rx()
169 writel(temp_reg, msp->registers + MSP_RCF); in set_prot_desc_rx()
172 static int configure_protocol(struct ux500_msp *msp, in configure_protocol() argument
180 msp->def_elem_len = config->def_elem_len; in configure_protocol()
183 dev_err(msp->dev, "%s: ERROR: Invalid protocol!\n", in configure_protocol()
194 dev_err(msp->dev, in configure_protocol()
201 set_prot_desc_tx(msp, protdesc, data_size); in configure_protocol()
203 set_prot_desc_rx(msp, protdesc, data_size); in configure_protocol()
206 temp_reg = readl(msp->registers + MSP_GCR) & ~TX_CLK_POL_RISING; in configure_protocol()
208 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
209 temp_reg = readl(msp->registers + MSP_GCR) & ~RX_CLK_POL_RISING; in configure_protocol()
211 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
216 static int setup_bitclk(struct ux500_msp *msp, struct ux500_msp_config *config) in setup_bitclk() argument
225 reg_val_GCR = readl(msp->registers + MSP_GCR); in setup_bitclk()
226 writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR); in setup_bitclk()
249 dev_err(msp->dev, "%s: ERROR: Unknown protocol (%d)!\n", in setup_bitclk()
258 writel(temp_reg, msp->registers + MSP_SRG); in setup_bitclk()
260 msp->f_bitclk = (config->f_inputclk)/(sck_div + 1); in setup_bitclk()
264 reg_val_GCR = readl(msp->registers + MSP_GCR); in setup_bitclk()
265 writel(reg_val_GCR | SRG_ENABLE, msp->registers + MSP_GCR); in setup_bitclk()
271 static int configure_multichannel(struct ux500_msp *msp, in configure_multichannel() argument
280 dev_err(msp->dev, in configure_multichannel()
294 reg_val_MCR = readl(msp->registers + MSP_MCR); in configure_multichannel()
297 msp->registers + MSP_MCR); in configure_multichannel()
299 msp->registers + MSP_TCE0); in configure_multichannel()
301 msp->registers + MSP_TCE1); in configure_multichannel()
303 msp->registers + MSP_TCE2); in configure_multichannel()
305 msp->registers + MSP_TCE3); in configure_multichannel()
307 dev_err(msp->dev, in configure_multichannel()
315 reg_val_MCR = readl(msp->registers + MSP_MCR); in configure_multichannel()
318 msp->registers + MSP_MCR); in configure_multichannel()
320 msp->registers + MSP_RCE0); in configure_multichannel()
322 msp->registers + MSP_RCE1); in configure_multichannel()
324 msp->registers + MSP_RCE2); in configure_multichannel()
326 msp->registers + MSP_RCE3); in configure_multichannel()
328 dev_err(msp->dev, in configure_multichannel()
334 reg_val_MCR = readl(msp->registers + MSP_MCR); in configure_multichannel()
337 msp->registers + MSP_MCR); in configure_multichannel()
340 msp->registers + MSP_RCM); in configure_multichannel()
342 msp->registers + MSP_RCV); in configure_multichannel()
350 static int enable_msp(struct ux500_msp *msp, struct ux500_msp_config *config) in enable_msp() argument
356 configure_protocol(msp, config); in enable_msp()
357 setup_bitclk(msp, config); in enable_msp()
359 status = configure_multichannel(msp, config); in enable_msp()
361 dev_warn(msp->dev, in enable_msp()
368 !msp->capture_dma_data.dma_cfg) { in enable_msp()
369 dev_err(msp->dev, "%s: ERROR: MSP RX-mode is not configured!", in enable_msp()
374 !msp->playback_dma_data.dma_cfg) { in enable_msp()
375 dev_err(msp->dev, "%s: ERROR: MSP TX-mode is not configured!", in enable_msp()
380 reg_val_DMACR = readl(msp->registers + MSP_DMACR); in enable_msp()
385 writel(reg_val_DMACR, msp->registers + MSP_DMACR); in enable_msp()
387 writel(config->iodelay, msp->registers + MSP_IODLY); in enable_msp()
390 reg_val_GCR = readl(msp->registers + MSP_GCR); in enable_msp()
391 writel(reg_val_GCR | FRAME_GEN_ENABLE, msp->registers + MSP_GCR); in enable_msp()
396 static void flush_fifo_rx(struct ux500_msp *msp) in flush_fifo_rx() argument
401 reg_val_GCR = readl(msp->registers + MSP_GCR); in flush_fifo_rx()
402 writel(reg_val_GCR | RX_ENABLE, msp->registers + MSP_GCR); in flush_fifo_rx()
404 reg_val_FLR = readl(msp->registers + MSP_FLR); in flush_fifo_rx()
406 readl(msp->registers + MSP_DR); in flush_fifo_rx()
407 reg_val_FLR = readl(msp->registers + MSP_FLR); in flush_fifo_rx()
410 writel(reg_val_GCR, msp->registers + MSP_GCR); in flush_fifo_rx()
413 static void flush_fifo_tx(struct ux500_msp *msp) in flush_fifo_tx() argument
418 reg_val_GCR = readl(msp->registers + MSP_GCR); in flush_fifo_tx()
419 writel(reg_val_GCR | TX_ENABLE, msp->registers + MSP_GCR); in flush_fifo_tx()
420 writel(MSP_ITCR_ITEN | MSP_ITCR_TESTFIFO, msp->registers + MSP_ITCR); in flush_fifo_tx()
422 reg_val_FLR = readl(msp->registers + MSP_FLR); in flush_fifo_tx()
424 readl(msp->registers + MSP_TSTDR); in flush_fifo_tx()
425 reg_val_FLR = readl(msp->registers + MSP_FLR); in flush_fifo_tx()
427 writel(0x0, msp->registers + MSP_ITCR); in flush_fifo_tx()
428 writel(reg_val_GCR, msp->registers + MSP_GCR); in flush_fifo_tx()
431 int ux500_msp_i2s_open(struct ux500_msp *msp, in ux500_msp_i2s_open() argument
439 dev_err(msp->dev, in ux500_msp_i2s_open()
448 dev_err(msp->dev, "%s: Error: No direction selected!\n", in ux500_msp_i2s_open()
453 tx_busy = (msp->dir_busy & MSP_DIR_TX) > 0; in ux500_msp_i2s_open()
454 rx_busy = (msp->dir_busy & MSP_DIR_RX) > 0; in ux500_msp_i2s_open()
456 dev_err(msp->dev, "%s: Error: TX is in use!\n", __func__); in ux500_msp_i2s_open()
460 dev_err(msp->dev, "%s: Error: RX is in use!\n", __func__); in ux500_msp_i2s_open()
464 msp->dir_busy |= (tx_sel ? MSP_DIR_TX : 0) | (rx_sel ? MSP_DIR_RX : 0); in ux500_msp_i2s_open()
479 old_reg = readl(msp->registers + MSP_GCR); in ux500_msp_i2s_open()
482 writel(new_reg, msp->registers + MSP_GCR); in ux500_msp_i2s_open()
484 res = enable_msp(msp, config); in ux500_msp_i2s_open()
486 dev_err(msp->dev, "%s: ERROR: enable_msp failed (%d)!\n", in ux500_msp_i2s_open()
491 msp->loopback_enable = 1; in ux500_msp_i2s_open()
494 flush_fifo_tx(msp); in ux500_msp_i2s_open()
495 flush_fifo_rx(msp); in ux500_msp_i2s_open()
497 msp->msp_state = MSP_STATE_CONFIGURED; in ux500_msp_i2s_open()
501 static void disable_msp_rx(struct ux500_msp *msp) in disable_msp_rx() argument
505 reg_val_GCR = readl(msp->registers + MSP_GCR); in disable_msp_rx()
506 writel(reg_val_GCR & ~RX_ENABLE, msp->registers + MSP_GCR); in disable_msp_rx()
507 reg_val_DMACR = readl(msp->registers + MSP_DMACR); in disable_msp_rx()
508 writel(reg_val_DMACR & ~RX_DMA_ENABLE, msp->registers + MSP_DMACR); in disable_msp_rx()
509 reg_val_IMSC = readl(msp->registers + MSP_IMSC); in disable_msp_rx()
512 msp->registers + MSP_IMSC); in disable_msp_rx()
514 msp->dir_busy &= ~MSP_DIR_RX; in disable_msp_rx()
517 static void disable_msp_tx(struct ux500_msp *msp) in disable_msp_tx() argument
521 reg_val_GCR = readl(msp->registers + MSP_GCR); in disable_msp_tx()
522 writel(reg_val_GCR & ~TX_ENABLE, msp->registers + MSP_GCR); in disable_msp_tx()
523 reg_val_DMACR = readl(msp->registers + MSP_DMACR); in disable_msp_tx()
524 writel(reg_val_DMACR & ~TX_DMA_ENABLE, msp->registers + MSP_DMACR); in disable_msp_tx()
525 reg_val_IMSC = readl(msp->registers + MSP_IMSC); in disable_msp_tx()
528 msp->registers + MSP_IMSC); in disable_msp_tx()
530 msp->dir_busy &= ~MSP_DIR_TX; in disable_msp_tx()
533 static int disable_msp(struct ux500_msp *msp, unsigned int dir) in disable_msp() argument
538 reg_val_GCR = readl(msp->registers + MSP_GCR); in disable_msp()
542 reg_val_GCR = readl(msp->registers + MSP_GCR); in disable_msp()
544 msp->registers + MSP_GCR); in disable_msp()
547 flush_fifo_tx(msp); in disable_msp()
550 writel((readl(msp->registers + MSP_GCR) & in disable_msp()
551 (~TX_ENABLE)), msp->registers + MSP_GCR); in disable_msp()
554 flush_fifo_rx(msp); in disable_msp()
557 writel((readl(msp->registers + MSP_GCR) & in disable_msp()
559 msp->registers + MSP_GCR); in disable_msp()
561 disable_msp_tx(msp); in disable_msp()
562 disable_msp_rx(msp); in disable_msp()
564 disable_msp_tx(msp); in disable_msp()
566 disable_msp_rx(msp); in disable_msp()
571 int ux500_msp_i2s_trigger(struct ux500_msp *msp, int cmd, int direction) in ux500_msp_i2s_trigger() argument
575 if (msp->msp_state == MSP_STATE_IDLE) { in ux500_msp_i2s_trigger()
576 dev_err(msp->dev, "%s: ERROR: MSP is not configured!\n", in ux500_msp_i2s_trigger()
589 reg_val_GCR = readl(msp->registers + MSP_GCR); in ux500_msp_i2s_trigger()
590 writel(reg_val_GCR | enable_bit, msp->registers + MSP_GCR); in ux500_msp_i2s_trigger()
597 disable_msp_tx(msp); in ux500_msp_i2s_trigger()
599 disable_msp_rx(msp); in ux500_msp_i2s_trigger()
608 int ux500_msp_i2s_close(struct ux500_msp *msp, unsigned int dir) in ux500_msp_i2s_close() argument
612 dev_dbg(msp->dev, "%s: Enter (dir = 0x%01x).\n", __func__, dir); in ux500_msp_i2s_close()
614 status = disable_msp(msp, dir); in ux500_msp_i2s_close()
615 if (msp->dir_busy == 0) { in ux500_msp_i2s_close()
617 msp->msp_state = MSP_STATE_IDLE; in ux500_msp_i2s_close()
618 writel((readl(msp->registers + MSP_GCR) & in ux500_msp_i2s_close()
620 msp->registers + MSP_GCR); in ux500_msp_i2s_close()
622 writel(0, msp->registers + MSP_GCR); in ux500_msp_i2s_close()
623 writel(0, msp->registers + MSP_TCF); in ux500_msp_i2s_close()
624 writel(0, msp->registers + MSP_RCF); in ux500_msp_i2s_close()
625 writel(0, msp->registers + MSP_DMACR); in ux500_msp_i2s_close()
626 writel(0, msp->registers + MSP_SRG); in ux500_msp_i2s_close()
627 writel(0, msp->registers + MSP_MCR); in ux500_msp_i2s_close()
628 writel(0, msp->registers + MSP_RCM); in ux500_msp_i2s_close()
629 writel(0, msp->registers + MSP_RCV); in ux500_msp_i2s_close()
630 writel(0, msp->registers + MSP_TCE0); in ux500_msp_i2s_close()
631 writel(0, msp->registers + MSP_TCE1); in ux500_msp_i2s_close()
632 writel(0, msp->registers + MSP_TCE2); in ux500_msp_i2s_close()
633 writel(0, msp->registers + MSP_TCE3); in ux500_msp_i2s_close()
634 writel(0, msp->registers + MSP_RCE0); in ux500_msp_i2s_close()
635 writel(0, msp->registers + MSP_RCE1); in ux500_msp_i2s_close()
636 writel(0, msp->registers + MSP_RCE2); in ux500_msp_i2s_close()
637 writel(0, msp->registers + MSP_RCE3); in ux500_msp_i2s_close()
645 struct ux500_msp *msp, in ux500_msp_i2s_of_init_msp() argument
657 msp->playback_dma_data.dma_cfg = devm_kzalloc(&pdev->dev, in ux500_msp_i2s_of_init_msp()
660 if (!msp->playback_dma_data.dma_cfg) in ux500_msp_i2s_of_init_msp()
663 msp->capture_dma_data.dma_cfg = devm_kzalloc(&pdev->dev, in ux500_msp_i2s_of_init_msp()
666 if (!msp->capture_dma_data.dma_cfg) in ux500_msp_i2s_of_init_msp()
678 struct ux500_msp *msp; in ux500_msp_i2s_init_msp() local
682 msp = *msp_p; in ux500_msp_i2s_init_msp()
683 if (!msp) in ux500_msp_i2s_init_msp()
688 ret = ux500_msp_i2s_of_init_msp(pdev, msp, in ux500_msp_i2s_init_msp()
695 msp->playback_dma_data.dma_cfg = platform_data->msp_i2s_dma_tx; in ux500_msp_i2s_init_msp()
696 msp->capture_dma_data.dma_cfg = platform_data->msp_i2s_dma_rx; in ux500_msp_i2s_init_msp()
697 msp->id = platform_data->id; in ux500_msp_i2s_init_msp()
700 msp->dev = &pdev->dev; in ux500_msp_i2s_init_msp()
709 msp->playback_dma_data.tx_rx_addr = res->start + MSP_DR; in ux500_msp_i2s_init_msp()
710 msp->capture_dma_data.tx_rx_addr = res->start + MSP_DR; in ux500_msp_i2s_init_msp()
712 msp->registers = devm_ioremap(&pdev->dev, res->start, in ux500_msp_i2s_init_msp()
714 if (msp->registers == NULL) { in ux500_msp_i2s_init_msp()
719 msp->msp_state = MSP_STATE_IDLE; in ux500_msp_i2s_init_msp()
720 msp->loopback_enable = 0; in ux500_msp_i2s_init_msp()
726 struct ux500_msp *msp) in ux500_msp_i2s_cleanup_msp() argument
728 dev_dbg(msp->dev, "%s: Enter (id = %d).\n", __func__, msp->id); in ux500_msp_i2s_cleanup_msp()