Lines Matching +full:num +full:- +full:lanes
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ALSA SoC Audio Layer - Rockchip SAI Controller driver
23 #define DRV_NAME "rockchip-sai"
68 .quirk = "rockchip,always-on",
79 if (sai->is_master_mode) in rockchip_sai_runtime_suspend()
80 regmap_update_bits(sai->regmap, SAI_XFER, in rockchip_sai_runtime_suspend()
86 ret = regmap_read_poll_timeout_atomic(sai->regmap, SAI_XFER, val, in rockchip_sai_runtime_suspend()
89 dev_warn(sai->dev, "Failed to idle FS\n"); in rockchip_sai_runtime_suspend()
91 regcache_cache_only(sai->regmap, true); in rockchip_sai_runtime_suspend()
104 * The max BCLK cycle time is: 31us @ 8K-8Bit (64K BCLK) in rockchip_sai_runtime_suspend()
107 clk_disable_unprepare(sai->mclk); in rockchip_sai_runtime_suspend()
108 clk_disable_unprepare(sai->hclk); in rockchip_sai_runtime_suspend()
118 ret = clk_prepare_enable(sai->hclk); in rockchip_sai_runtime_resume()
122 ret = clk_prepare_enable(sai->mclk); in rockchip_sai_runtime_resume()
126 regcache_cache_only(sai->regmap, false); in rockchip_sai_runtime_resume()
127 regcache_mark_dirty(sai->regmap); in rockchip_sai_runtime_resume()
128 ret = regcache_sync(sai->regmap); in rockchip_sai_runtime_resume()
132 if (sai->quirks & QUIRK_ALWAYS_ON && sai->is_master_mode) in rockchip_sai_runtime_resume()
133 regmap_update_bits(sai->regmap, SAI_XFER, in rockchip_sai_runtime_resume()
142 clk_disable_unprepare(sai->mclk); in rockchip_sai_runtime_resume()
144 clk_disable_unprepare(sai->hclk); in rockchip_sai_runtime_resume()
154 regmap_update_bits(sai->regmap, SAI_INTCR, in rockchip_sai_fifo_xrun_detect()
156 regmap_update_bits(sai->regmap, SAI_INTCR, in rockchip_sai_fifo_xrun_detect()
161 regmap_update_bits(sai->regmap, SAI_INTCR, in rockchip_sai_fifo_xrun_detect()
163 regmap_update_bits(sai->regmap, SAI_INTCR, in rockchip_sai_fifo_xrun_detect()
176 regmap_update_bits(sai->regmap, SAI_DMACR, in rockchip_sai_dma_ctrl()
180 regmap_update_bits(sai->regmap, SAI_DMACR, in rockchip_sai_dma_ctrl()
200 reset_control_assert(sai->rst_h); in rockchip_sai_reset()
203 reset_control_deassert(sai->rst_h); in rockchip_sai_reset()
206 reset_control_assert(sai->rst_m); in rockchip_sai_reset()
209 reset_control_deassert(sai->rst_m); in rockchip_sai_reset()
214 regcache_mark_dirty(sai->regmap); in rockchip_sai_reset()
215 regcache_sync(sai->regmap); in rockchip_sai_reset()
223 regmap_update_bits(sai->regmap, SAI_CLR, clr, clr); in rockchip_sai_clear()
224 ret = regmap_read_poll_timeout_atomic(sai->regmap, SAI_CLR, val, in rockchip_sai_clear()
227 dev_warn(sai->dev, "Failed to clear %u\n", clr); in rockchip_sai_clear()
242 regmap_update_bits(sai->regmap, SAI_XFER, in rockchip_sai_xfer_start()
246 regmap_update_bits(sai->regmap, SAI_XFER, in rockchip_sai_xfer_start()
269 regmap_update_bits(sai->regmap, SAI_XFER, msk, val); in rockchip_sai_xfer_stop()
270 ret = regmap_read_poll_timeout_atomic(sai->regmap, SAI_XFER, val, in rockchip_sai_xfer_stop()
273 dev_warn(sai->dev, "Failed to idle stream %d\n", stream); in rockchip_sai_xfer_stop()
303 sai->fpw = FPW_HALF_FRAME_WIDTH; in rockchip_sai_fmt_create()
312 sai->fpw = FPW_HALF_FRAME_WIDTH; in rockchip_sai_fmt_create()
321 sai->fpw = FPW_HALF_FRAME_WIDTH; in rockchip_sai_fmt_create()
330 sai->fpw = FPW_ONE_BCLK_WIDTH; in rockchip_sai_fmt_create()
339 sai->fpw = FPW_ONE_BCLK_WIDTH; in rockchip_sai_fmt_create()
342 dev_err(sai->dev, "Unsupported fmt %u\n", fmt); in rockchip_sai_fmt_create()
346 regmap_update_bits(sai->regmap, SAI_TXCR, xcr_mask, xcr_val); in rockchip_sai_fmt_create()
347 regmap_update_bits(sai->regmap, SAI_RXCR, xcr_mask, xcr_val); in rockchip_sai_fmt_create()
348 regmap_update_bits(sai->regmap, SAI_TX_SHIFT, xsft_mask, xsft_val); in rockchip_sai_fmt_create()
349 regmap_update_bits(sai->regmap, SAI_RX_SHIFT, xsft_mask, xsft_val); in rockchip_sai_fmt_create()
350 regmap_update_bits(sai->regmap, SAI_FSCR, fscr_mask, fscr_val); in rockchip_sai_fmt_create()
359 pm_runtime_get_sync(dai->dev); in rockchip_sai_set_fmt()
364 sai->is_master_mode = true; in rockchip_sai_set_fmt()
368 sai->is_master_mode = false; in rockchip_sai_set_fmt()
371 ret = -EINVAL; in rockchip_sai_set_fmt()
375 regmap_update_bits(sai->regmap, SAI_CKR, mask, val); in rockchip_sai_set_fmt()
392 ret = -EINVAL; in rockchip_sai_set_fmt()
396 regmap_update_bits(sai->regmap, SAI_CKR, mask, val); in rockchip_sai_set_fmt()
401 pm_runtime_put(dai->dev); in rockchip_sai_set_fmt()
410 unsigned int lanes = 1; in rockchip_sai_lanes_auto() local
412 if (!sai->is_tdm) in rockchip_sai_lanes_auto()
413 lanes = DIV_ROUND_UP(params_channels(params), 2); in rockchip_sai_lanes_auto()
415 return lanes; in rockchip_sai_lanes_auto()
425 unsigned int ch_per_lane, lanes, slot_width; in rockchip_sai_hw_params() local
429 dma_data->maxburst = MAXBURST_PER_FIFO * params_channels(params) / 2; in rockchip_sai_hw_params()
431 lanes = rockchip_sai_lanes_auto(params, dai); in rockchip_sai_hw_params()
433 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { in rockchip_sai_hw_params()
435 if (sai->tx_lanes) in rockchip_sai_hw_params()
436 lanes = sai->tx_lanes; in rockchip_sai_hw_params()
439 if (sai->rx_lanes) in rockchip_sai_hw_params()
440 lanes = sai->rx_lanes; in rockchip_sai_hw_params()
459 return -EINVAL; in rockchip_sai_hw_params()
462 val |= SAI_XCR_CSR(lanes); in rockchip_sai_hw_params()
464 regmap_update_bits(sai->regmap, reg, SAI_XCR_VDW_MASK | SAI_XCR_CSR_MASK, val); in rockchip_sai_hw_params()
466 regmap_read(sai->regmap, reg, &val); in rockchip_sai_hw_params()
469 ch_per_lane = params_channels(params) / lanes; in rockchip_sai_hw_params()
471 regmap_update_bits(sai->regmap, reg, SAI_XCR_SNB_MASK, in rockchip_sai_hw_params()
474 fscr = SAI_FSCR_FW(sai->fw_ratio * slot_width * ch_per_lane); in rockchip_sai_hw_params()
476 switch (sai->fpw) { in rockchip_sai_hw_params()
484 fscr |= SAI_FSCR_FPW(sai->fw_ratio * slot_width * ch_per_lane / 2); in rockchip_sai_hw_params()
487 dev_err(sai->dev, "Invalid Frame Pulse Width %d\n", sai->fpw); in rockchip_sai_hw_params()
488 return -EINVAL; in rockchip_sai_hw_params()
491 regmap_update_bits(sai->regmap, SAI_FSCR, in rockchip_sai_hw_params()
494 if (sai->is_master_mode) { in rockchip_sai_hw_params()
495 bclk_rate = sai->fw_ratio * slot_width * ch_per_lane * params_rate(params); in rockchip_sai_hw_params()
496 if (sai->is_clk_auto) in rockchip_sai_hw_params()
497 clk_set_rate(sai->mclk, bclk_rate); in rockchip_sai_hw_params()
498 mclk_rate = clk_get_rate(sai->mclk); in rockchip_sai_hw_params()
500 dev_err(sai->dev, "Mismatch mclk: %u, expected %u at least\n", in rockchip_sai_hw_params()
502 return -EINVAL; in rockchip_sai_hw_params()
507 regmap_update_bits(sai->regmap, SAI_CKR, SAI_CKR_MDIV_MASK, in rockchip_sai_hw_params()
519 if (sai->is_master_mode) { in rockchip_sai_prepare()
528 * The max BCLK cycle time is: 15.6us @ 8K-8Bit (64K BCLK) in rockchip_sai_prepare()
531 regmap_update_bits(sai->regmap, SAI_XFER, in rockchip_sai_prepare()
551 rockchip_sai_start(sai, substream->stream); in rockchip_sai_trigger()
556 rockchip_sai_stop(sai, substream->stream); in rockchip_sai_trigger()
559 ret = -EINVAL; in rockchip_sai_trigger()
572 if (!freq || sai->is_clk_auto) in rockchip_sai_set_sysclk()
575 ret = clk_set_rate(sai->mclk, freq); in rockchip_sai_set_sysclk()
577 dev_err(sai->dev, "Failed to set mclk %d\n", ret); in rockchip_sai_set_sysclk()
587 sai->has_playback ? &sai->playback_dma_data : NULL, in rockchip_sai_dai_probe()
588 sai->has_capture ? &sai->capture_dma_data : NULL); in rockchip_sai_dai_probe()
597 int stream = substream->stream; in rockchip_sai_startup()
599 if (sai->substreams[stream]) in rockchip_sai_startup()
600 return -EBUSY; in rockchip_sai_startup()
602 if (sai->wait_time[stream]) in rockchip_sai_startup()
603 substream->wait_time = msecs_to_jiffies(sai->wait_time[stream]); in rockchip_sai_startup()
605 sai->substreams[stream] = substream; in rockchip_sai_startup()
615 sai->substreams[substream->stream] = NULL; in rockchip_sai_shutdown()
624 pm_runtime_get_sync(dai->dev); in rockchip_sai_set_tdm_slot()
625 regmap_update_bits(sai->regmap, SAI_TXCR, SAI_XCR_SBW_MASK, in rockchip_sai_set_tdm_slot()
627 regmap_update_bits(sai->regmap, SAI_RXCR, SAI_XCR_SBW_MASK, in rockchip_sai_set_tdm_slot()
629 pm_runtime_put(dai->dev); in rockchip_sai_set_tdm_slot()
631 sai->is_tdm = true; in rockchip_sai_set_tdm_slot()
771 { .compatible = "rockchip,sai-v1", },
778 struct device_node *node = sai->dev->of_node; in rockchip_sai_init_dai()
783 of_property_for_each_string(node, "dma-names", dma_names, dma_name) { in rockchip_sai_init_dai()
785 sai->has_playback = true; in rockchip_sai_init_dai()
787 sai->has_capture = true; in rockchip_sai_init_dai()
790 dai = devm_kmemdup(sai->dev, &rockchip_sai_dai, in rockchip_sai_init_dai()
793 return -ENOMEM; in rockchip_sai_init_dai()
795 if (sai->has_playback) { in rockchip_sai_init_dai()
796 dai->playback.stream_name = "Playback"; in rockchip_sai_init_dai()
797 dai->playback.channels_min = 1; in rockchip_sai_init_dai()
798 dai->playback.channels_max = 128; in rockchip_sai_init_dai()
799 dai->playback.rates = SNDRV_PCM_RATE_8000_192000; in rockchip_sai_init_dai()
800 dai->playback.formats = SNDRV_PCM_FMTBIT_S8 | in rockchip_sai_init_dai()
806 sai->playback_dma_data.addr = res->start + SAI_TXDR; in rockchip_sai_init_dai()
807 sai->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; in rockchip_sai_init_dai()
808 sai->playback_dma_data.maxburst = MAXBURST_PER_FIFO; in rockchip_sai_init_dai()
811 if (sai->has_capture) { in rockchip_sai_init_dai()
812 dai->capture.stream_name = "Capture"; in rockchip_sai_init_dai()
813 dai->capture.channels_min = 1; in rockchip_sai_init_dai()
814 dai->capture.channels_max = 128; in rockchip_sai_init_dai()
815 dai->capture.rates = SNDRV_PCM_RATE_8000_192000; in rockchip_sai_init_dai()
816 dai->capture.formats = SNDRV_PCM_FMTBIT_S8 | in rockchip_sai_init_dai()
822 sai->capture_dma_data.addr = res->start + SAI_RXDR; in rockchip_sai_init_dai()
823 sai->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; in rockchip_sai_init_dai()
824 sai->capture_dma_data.maxburst = MAXBURST_PER_FIFO; in rockchip_sai_init_dai()
827 regmap_update_bits(sai->regmap, SAI_DMACR, SAI_DMACR_TDL_MASK, in rockchip_sai_init_dai()
829 regmap_update_bits(sai->regmap, SAI_DMACR, SAI_DMACR_RDL_MASK, in rockchip_sai_init_dai()
940 ucontrol->value.enumerated.item[0] = sai->fpw; in rockchip_sai_fpw_get()
950 int num; in rockchip_sai_fpw_put() local
952 num = ucontrol->value.enumerated.item[0]; in rockchip_sai_fpw_put()
953 if (num >= ARRAY_SIZE(fpw_text)) in rockchip_sai_fpw_put()
954 return -EINVAL; in rockchip_sai_fpw_put()
956 sai->fpw = num; in rockchip_sai_fpw_put()
967 ucontrol->value.enumerated.item[0] = sai->fw_ratio - 1; in rockchip_sai_fw_ratio_get()
977 int ratio = ucontrol->value.enumerated.item[0] + 1; in rockchip_sai_fw_ratio_put()
980 return -EINVAL; in rockchip_sai_fw_ratio_put()
982 sai->fw_ratio = ratio; in rockchip_sai_fw_ratio_put()
993 ucontrol->value.enumerated.item[0] = sai->tx_lanes; in rockchip_sai_tx_lanes_get()
1003 int num; in rockchip_sai_tx_lanes_put() local
1005 num = ucontrol->value.enumerated.item[0]; in rockchip_sai_tx_lanes_put()
1006 if (num >= ARRAY_SIZE(tx_lanes_text)) in rockchip_sai_tx_lanes_put()
1007 return -EINVAL; in rockchip_sai_tx_lanes_put()
1009 sai->tx_lanes = num; in rockchip_sai_tx_lanes_put()
1020 ucontrol->value.enumerated.item[0] = sai->rx_lanes; in rockchip_sai_rx_lanes_get()
1030 int num; in rockchip_sai_rx_lanes_put() local
1032 num = ucontrol->value.enumerated.item[0]; in rockchip_sai_rx_lanes_put()
1033 if (num >= ARRAY_SIZE(rx_lanes_text)) in rockchip_sai_rx_lanes_put()
1034 return -EINVAL; in rockchip_sai_rx_lanes_put()
1036 sai->rx_lanes = num; in rockchip_sai_rx_lanes_put()
1047 ucontrol->value.enumerated.item[0] = sai->is_master_mode; in rockchip_sai_mss_get()
1061 return -EPERM; in rockchip_sai_mss_put()
1063 mss = !!ucontrol->value.enumerated.item[0]; in rockchip_sai_mss_put()
1064 if (mss == sai->is_master_mode) in rockchip_sai_mss_put()
1067 sai->is_master_mode = mss; in rockchip_sai_mss_put()
1069 pm_runtime_get_sync(sai->dev); in rockchip_sai_mss_put()
1070 if (sai->is_master_mode) { in rockchip_sai_mss_put()
1072 regmap_update_bits(sai->regmap, SAI_CKR, in rockchip_sai_mss_put()
1075 regmap_update_bits(sai->regmap, SAI_XFER, in rockchip_sai_mss_put()
1082 regmap_update_bits(sai->regmap, SAI_CKR, in rockchip_sai_mss_put()
1085 regmap_update_bits(sai->regmap, SAI_XFER, in rockchip_sai_mss_put()
1091 pm_runtime_put(sai->dev); in rockchip_sai_mss_put()
1102 ucontrol->value.integer.value[0] = sai->is_clk_auto; in rockchip_sai_clk_auto_get()
1112 bool clk_auto = ucontrol->value.integer.value[0]; in rockchip_sai_clk_auto_put()
1114 if (clk_auto == sai->is_clk_auto) in rockchip_sai_clk_auto_put()
1117 sai->is_clk_auto = clk_auto; in rockchip_sai_clk_auto_put()
1125 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; in rockchip_sai_wait_time_info()
1126 uinfo->count = 1; in rockchip_sai_wait_time_info()
1127 uinfo->value.integer.min = 0; in rockchip_sai_wait_time_info()
1128 uinfo->value.integer.max = WAIT_TIME_MS_MAX; in rockchip_sai_wait_time_info()
1129 uinfo->value.integer.step = 1; in rockchip_sai_wait_time_info()
1140 ucontrol->value.integer.value[0] = sai->wait_time[SNDRV_PCM_STREAM_CAPTURE]; in rockchip_sai_rd_wait_time_get()
1151 if (ucontrol->value.integer.value[0] > WAIT_TIME_MS_MAX) in rockchip_sai_rd_wait_time_put()
1152 return -EINVAL; in rockchip_sai_rd_wait_time_put()
1154 sai->wait_time[SNDRV_PCM_STREAM_CAPTURE] = ucontrol->value.integer.value[0]; in rockchip_sai_rd_wait_time_put()
1165 ucontrol->value.integer.value[0] = sai->wait_time[SNDRV_PCM_STREAM_PLAYBACK]; in rockchip_sai_wr_wait_time_get()
1176 if (ucontrol->value.integer.value[0] > WAIT_TIME_MS_MAX) in rockchip_sai_wr_wait_time_put()
1177 return -EINVAL; in rockchip_sai_wr_wait_time_put()
1179 sai->wait_time[SNDRV_PCM_STREAM_PLAYBACK] = ucontrol->value.integer.value[0]; in rockchip_sai_wr_wait_time_put()
1273 regmap_read(sai->regmap, SAI_INTSR, &val); in rockchip_sai_isr()
1275 dev_warn_ratelimited(sai->dev, "TX FIFO Underrun\n"); in rockchip_sai_isr()
1276 regmap_update_bits(sai->regmap, SAI_INTCR, in rockchip_sai_isr()
1278 substream = sai->substreams[SNDRV_PCM_STREAM_PLAYBACK]; in rockchip_sai_isr()
1284 dev_warn_ratelimited(sai->dev, "RX FIFO Overrun\n"); in rockchip_sai_isr()
1285 regmap_update_bits(sai->regmap, SAI_INTCR, in rockchip_sai_isr()
1287 substream = sai->substreams[SNDRV_PCM_STREAM_CAPTURE]; in rockchip_sai_isr()
1299 sai->is_master_mode = true; in rockchip_sai_keep_clk_always_on()
1304 regmap_update_bits(sai->regmap, SAI_FSCR, in rockchip_sai_keep_clk_always_on()
1310 mclk_rate = clk_get_rate(sai->mclk); in rockchip_sai_keep_clk_always_on()
1314 regmap_update_bits(sai->regmap, SAI_CKR, SAI_CKR_MDIV_MASK, in rockchip_sai_keep_clk_always_on()
1317 pm_runtime_forbid(sai->dev); in rockchip_sai_keep_clk_always_on()
1319 dev_info(sai->dev, "CLK-ALWAYS-ON: mclk: %d, bclk: %d, fsync: %d\n", in rockchip_sai_keep_clk_always_on()
1330 if (device_property_read_bool(sai->dev, of_quirks[i].quirk)) in rockchip_sai_parse_quirks()
1331 sai->quirks |= of_quirks[i].id; in rockchip_sai_parse_quirks()
1333 if (sai->quirks & QUIRK_ALWAYS_ON) in rockchip_sai_parse_quirks()
1341 struct device_node *node = pdev->dev.of_node; in rockchip_sai_probe()
1348 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); in rockchip_sai_probe()
1350 return -ENOMEM; in rockchip_sai_probe()
1352 sai->dev = &pdev->dev; in rockchip_sai_probe()
1353 sai->fw_ratio = 1; in rockchip_sai_probe()
1355 sai->is_master_mode = true; in rockchip_sai_probe()
1356 dev_set_drvdata(&pdev->dev, sai); in rockchip_sai_probe()
1358 sai->rst_h = devm_reset_control_get_optional_exclusive(&pdev->dev, "h"); in rockchip_sai_probe()
1359 if (IS_ERR(sai->rst_h)) in rockchip_sai_probe()
1360 return PTR_ERR(sai->rst_h); in rockchip_sai_probe()
1362 sai->rst_m = devm_reset_control_get_optional_exclusive(&pdev->dev, "m"); in rockchip_sai_probe()
1363 if (IS_ERR(sai->rst_m)) in rockchip_sai_probe()
1364 return PTR_ERR(sai->rst_m); in rockchip_sai_probe()
1370 sai->regmap = devm_regmap_init_mmio(&pdev->dev, regs, in rockchip_sai_probe()
1372 if (IS_ERR(sai->regmap)) in rockchip_sai_probe()
1373 return PTR_ERR(sai->regmap); in rockchip_sai_probe()
1377 ret = devm_request_irq(&pdev->dev, irq, rockchip_sai_isr, in rockchip_sai_probe()
1378 IRQF_SHARED, node->name, sai); in rockchip_sai_probe()
1380 dev_err(&pdev->dev, "Failed to request irq %d\n", irq); in rockchip_sai_probe()
1385 sai->mclk = devm_clk_get(&pdev->dev, "mclk"); in rockchip_sai_probe()
1386 if (IS_ERR(sai->mclk)) { in rockchip_sai_probe()
1387 dev_err(&pdev->dev, "Failed to get mclk\n"); in rockchip_sai_probe()
1388 return PTR_ERR(sai->mclk); in rockchip_sai_probe()
1391 sai->hclk = devm_clk_get(&pdev->dev, "hclk"); in rockchip_sai_probe()
1392 if (IS_ERR(sai->hclk)) { in rockchip_sai_probe()
1393 dev_err(&pdev->dev, "Failed to get hclk\n"); in rockchip_sai_probe()
1394 return PTR_ERR(sai->hclk); in rockchip_sai_probe()
1401 pm_runtime_enable(&pdev->dev); in rockchip_sai_probe()
1402 if (!pm_runtime_enabled(&pdev->dev)) { in rockchip_sai_probe()
1403 ret = rockchip_sai_runtime_resume(&pdev->dev); in rockchip_sai_probe()
1412 ret = devm_snd_soc_register_component(&pdev->dev, in rockchip_sai_probe()
1418 if (device_property_read_bool(&pdev->dev, "rockchip,no-dmaengine")) { in rockchip_sai_probe()
1419 dev_info(&pdev->dev, "Used for Multi-DAI\n"); in rockchip_sai_probe()
1423 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); in rockchip_sai_probe()
1430 if (!pm_runtime_status_suspended(&pdev->dev)) in rockchip_sai_probe()
1431 rockchip_sai_runtime_suspend(&pdev->dev); in rockchip_sai_probe()
1433 pm_runtime_disable(&pdev->dev); in rockchip_sai_probe()
1440 pm_runtime_disable(&pdev->dev); in rockchip_sai_remove()
1441 if (!pm_runtime_status_suspended(&pdev->dev)) in rockchip_sai_remove()
1442 rockchip_sai_runtime_suspend(&pdev->dev); in rockchip_sai_remove()
1464 MODULE_AUTHOR("Sugar Zhang <sugar.zhang@rock-chips.com>");