46 	0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
52 	0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
59 /*	0x0  0x1  0x2  0x3  0x4  0x5  0x6  0x7  0x8  0x9  0xa  0xb  0xc  0xd  0xe  0xf */
60 	0x0, 0x1, 0x2, 0x7, 0x4, 0x5, 0x6, 0x3, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xe, 0xd,
61 	0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
62 	0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
66 /*	0x0  0x1  0x2  0x3  0x4  0x5  0x6  0x7  0x8  0x9  0xa  0xb  0xc  0xd  0xe  0xf */
67 	0x8, 0x9, 0xa, 0x7, 0xc, 0x5, 0x6, 0xb, 0x0, 0x1, 0x2, 0x3, 0x4, 0xf, 0xe, 0xd,
68 	0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
69 	0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
74  * clk_map_imx8qm[0] is for i.MX8QM asrc0
76  * clk_map_imx8qxp[0] is for i.MX8QXP asrc0
81 	0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0,
82 	0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
83 	0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
86 	0xf, 0xf, 0xf, 0xf, 0xf, 0x7, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0,
87 	0x0, 0x1, 0x2, 0x3, 0xb, 0xc, 0xf, 0xf, 0xd, 0xe, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
88 	0x4, 0x5, 0x6, 0xf, 0x8, 0x9, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
94 	0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0,
95 	0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0xf, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xf,
96 	0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
99 	0xf, 0xf, 0xf, 0xf, 0xf, 0x7, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0,
100 	0x0, 0x1, 0x2, 0x3, 0x7, 0x8, 0xf, 0xf, 0x9, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
101 	0xf, 0xf, 0x6, 0xf, 0xf, 0xf, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
129 		*div = 0;  in fsl_asrc_divider_avail()
131 	if (clk_rate == 0 || rate == 0)  in fsl_asrc_divider_avail()
140 	if (rem != 0)  in fsl_asrc_divider_avail()
143 	for (i = 0; i < DIVIDER_NUM; i++) {  in fsl_asrc_divider_avail()
173 	/* select pre_proc between [0, 2] */  in fsl_asrc_sel_proc()
182 		*pre_proc = 0;  in fsl_asrc_sel_proc()
196 		*post_proc = 0;  in fsl_asrc_sel_proc()
216 	int i, ret = 0;  in fsl_asrc_request_pair()
262 			   ASRCTR_ASRCEi_MASK(index), 0);  in fsl_asrc_release_pair()
268 	pair->error = 0;  in fsl_asrc_release_pair()
304 	/* Calculate the divisors: prescaler [2^0, 2^7], divder [1, 8] */  in fsl_asrc_cal_asrck_divisor()
305 	for (ps = 0; div > 8; ps++)  in fsl_asrc_cal_asrck_divisor()
354 	return 0;  in fsl_asrc_set_ideal_ratio()
435 	for (in = 0; in < ARRAY_SIZE(supported_asrc_rate); in++)  in fsl_asrc_config_pair()
444 	for (out = 0; out < ARRAY_SIZE(supported_asrc_rate); out++)  in fsl_asrc_config_pair()
477 	if (div[IN] == 0 || (!ideal && !div_avail)) {  in fsl_asrc_config_pair()
493 	if (div[OUT] == 0 || (!ideal && !div_avail)) {  in fsl_asrc_config_pair()
516 			   ASRCTR_USRi_MASK(index), 0);  in fsl_asrc_config_pair()
550 		return 0;  in fsl_asrc_config_pair()
554 			   ASRCTR_ATSi_MASK(index), 0);  in fsl_asrc_config_pair()
597 	for (i = 0; i < pair->channels * 4; i++)  in fsl_asrc_start_pair()
598 		regmap_write(asrc->regmap, REG_ASRDI(index), 0);  in fsl_asrc_start_pair()
615 			   ASRCTR_ASRCEi_MASK(index), 0);  in fsl_asrc_stop_pair()
643 		snd_pcm_hw_constraint_step(substream->runtime, 0,  in fsl_asrc_dai_startup()
647 	return snd_pcm_hw_constraint_list(substream->runtime, 0,  in fsl_asrc_dai_startup()
661 	int i = 0, j = 0;  in fsl_asrc_select_clk()
667 	for (j = 0; j < 2; j++) {  in fsl_asrc_select_clk()
668 		for (i = 0; i < ASRC_CLK_MAP_LEN; i++) {  in fsl_asrc_select_clk()
736 	return 0;  in fsl_asrc_dai_hw_params()
748 	return 0;  in fsl_asrc_dai_hw_free()
772 	return 0;  in fsl_asrc_dai_trigger()
789 	return 0;  in fsl_asrc_dai_probe()
926 	{ REG_ASRCTR, 0x0000 }, { REG_ASRIER, 0x0000 },
927 	{ REG_ASRCNCR, 0x0000 }, { REG_ASRCFG, 0x0000 },
928 	{ REG_ASRCSR, 0x0000 }, { REG_ASRCDR1, 0x0000 },
929 	{ REG_ASRCDR2, 0x0000 }, { REG_ASRSTR, 0x0000 },
930 	{ REG_ASRRA, 0x0000 }, { REG_ASRRB, 0x0000 },
931 	{ REG_ASRRC, 0x0000 }, { REG_ASRPM1, 0x0000 },
932 	{ REG_ASRPM2, 0x0000 }, { REG_ASRPM3, 0x0000 },
933 	{ REG_ASRPM4, 0x0000 }, { REG_ASRPM5, 0x0000 },
934 	{ REG_ASRTFR1, 0x0000 }, { REG_ASRCCR, 0x0000 },
935 	{ REG_ASRDIA, 0x0000 }, { REG_ASRDOA, 0x0000 },
936 	{ REG_ASRDIB, 0x0000 }, { REG_ASRDOB, 0x0000 },
937 	{ REG_ASRDIC, 0x0000 }, { REG_ASRDOC, 0x0000 },
938 	{ REG_ASRIDRHA, 0x0000 }, { REG_ASRIDRLA, 0x0000 },
939 	{ REG_ASRIDRHB, 0x0000 }, { REG_ASRIDRLB, 0x0000 },
940 	{ REG_ASRIDRHC, 0x0000 }, { REG_ASRIDRLC, 0x0000 },
941 	{ REG_ASR76K, 0x0A47 }, { REG_ASR56K, 0x0DF3 },
942 	{ REG_ASRMCRA, 0x0000 }, { REG_ASRFSTA, 0x0000 },
943 	{ REG_ASRMCRB, 0x0000 }, { REG_ASRFSTB, 0x0000 },
944 	{ REG_ASRMCRC, 0x0000 }, { REG_ASRFSTC, 0x0000 },
945 	{ REG_ASRMCR1A, 0x0000 }, { REG_ASRMCR1B, 0x0000 },
946 	{ REG_ASRMCR1C, 0x0000 },
975 	regmap_write(asrc->regmap, REG_ASRIER, 0x0);  in fsl_asrc_init()
978 	regmap_write(asrc->regmap, REG_ASRPM1, 0x7fffff);  in fsl_asrc_init()
979 	regmap_write(asrc->regmap, REG_ASRPM2, 0x255555);  in fsl_asrc_init()
980 	regmap_write(asrc->regmap, REG_ASRPM3, 0xff7280);  in fsl_asrc_init()
981 	regmap_write(asrc->regmap, REG_ASRPM4, 0xff7280);  in fsl_asrc_init()
982 	regmap_write(asrc->regmap, REG_ASRPM5, 0xff7280);  in fsl_asrc_init()
984 	/* Base address for task queue FIFO. Set to 0x7C */  in fsl_asrc_init()
986 			   ASRTFR1_TF_BASE_MASK, ASRTFR1_TF_BASE(0xfc));  in fsl_asrc_init()
991 	 * On iMX6, ipg_clk = 133MHz, REG_ASR76K = 0x06D6, REG_ASR56K = 0x0947  in fsl_asrc_init()
1082 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);  in fsl_asrc_probe()
1096 	irq = platform_get_irq(pdev, 0);  in fsl_asrc_probe()
1097 	if (irq < 0)  in fsl_asrc_probe()
1100 	ret = devm_request_irq(&pdev->dev, irq, fsl_asrc_isr, 0,  in fsl_asrc_probe()
1123 	for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {  in fsl_asrc_probe()
1227 	return 0;  in fsl_asrc_probe()
1249 	for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {  in fsl_asrc_runtime_resume()
1258 			   ASRCTR_ASRCEi_ALL_MASK, 0);  in fsl_asrc_runtime_resume()
1273 	return 0;  in fsl_asrc_runtime_resume()
1276 	for (i--; i >= 0; i--)  in fsl_asrc_runtime_resume()
1298 	for (i = 0; i < ASRC_CLK_MAX_NUM; i++)  in fsl_asrc_runtime_suspend()
1305 	return 0;  in fsl_asrc_runtime_suspend()