soc/codecs/sgtl5000.c

114 	SGTL5000_MICBIAS_2K = 2,
239 	 * Don't clear VAG_POWERUP if 2 or more consumers of VAG present:  in vag_power_off()
245 	if (vag_power_consumers(component, ana_pwr, source) >= 2)  in vag_power_off()
262  * 0x1 = 2Kohm
377 			    SGTL5000_CHIP_ANA_CTRL, 2,
511 	uinfo->count = 2;  in dac_info_volsw()
625  * avc_put_threshold function: register_value = 10^(dB/20) * 0.636 * 2^15 ==>
660  *                                    register_value = 10^(dB/20) * 0.636 * 2^15
754 	SOC_SINGLE_TLV("AVC Max Gain Volume", SGTL5000_DAP_AVC_CTRL, 12, 2, 0,
767 	SOC_SINGLE_TLV("BASS 2", SGTL5000_DAP_EQ_BASS_BAND2,
881  * sgtl5000 provides 2 clock sources:
884  * 2. pll: can derive any audio clocks.
888  * 2. as constraint by sys_mclk, sample freq should be set to 32 kHz, 44.1 kHz
922 	case 2:  in sgtl5000_set_clock()
985 	/* if using pll, please check manual 6.4.2 for detail */  in sgtl5000_set_clock()
994 			in = sgtl5000->sysclk / 2;  in sgtl5000_set_clock()
1174 		.channels_max = 2,
1185 		.channels_max = 2,
1280  * 1. VAG, normally set to vdda/2
1281  * 2. charge pump, set to different value
1283  * 3. line out VAG, normally set to vddio/2
1287  * 2. vdda and vddio voltage value. > 3.1v or not
1361 	 * set ADC/DAC VAG to vdda / 2,  in sgtl5000_set_power_regs()
1364 	vag = vdda / 2;  in sgtl5000_set_power_regs()
1376 	/* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */  in sgtl5000_set_power_regs()
1377 	lo_vag = vddio / 2;  in sgtl5000_set_power_regs()
1545 	.reg_stride = 2,
1732 				sgtl5000->micbias_resistor = 2;  in sgtl5000_i2c_probe()
1738 				sgtl5000->micbias_resistor = 2;  in sgtl5000_i2c_probe()
1743 			/* default is 4Kohms */  in sgtl5000_i2c_probe()
1744 			sgtl5000->micbias_resistor = 2;  in sgtl5000_i2c_probe()