Lines Matching +full:6 +full:- +full:14
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5645.h -- RT5645 ALSA SoC audio driver
19 /* I/O - Output */
24 /* I/O - Input */
32 /* I/O - ADC/DAC/DMIC */
40 /* Mixer - D-D */
49 /* Mixer - PDM */
51 /* Mixer - ADC */
56 /* Mixer - DAC */
94 /* Format - ADC/DAC */
101 /* Format - TDM Control */
107 /* Function - Analog */
123 /* Function - Digital */
221 #define RT5645_VOL_L_MUTE (0x1 << 14)
222 #define RT5645_VOL_L_SFT 14
225 #define RT5645_VOL_R_MUTE (0x1 << 6)
226 #define RT5645_VOL_R_SFT 6
238 #define RT5645_CBJ_MIC_SEL_R (0x1 << 6)
250 #define RT5645_CBJ_TIE_G_R (0x1 << 14)
257 #define RT5645_IN_DF2 (0x1 << 6)
258 #define RT5645_IN_SFT2 6
309 #define RT5645_STO1_ADC_L_BST_MASK (0x3 << 14)
310 #define RT5645_STO1_ADC_L_BST_SFT 14
317 #define RT5645_MONO_ADC_L_BST_MASK (0x3 << 14)
318 #define RT5645_MONO_ADC_L_BST_SFT 14
329 #define RT5645_M_ADC_L1 (0x1 << 14)
330 #define RT5645_M_ADC_L1_SFT 14
341 #define RT5645_M_ADC_R1 (0x1 << 6)
342 #define RT5645_M_ADC_R1_SFT 6
349 #define RT5645_M_MONO_ADC_L1 (0x1 << 14)
350 #define RT5645_M_MONO_ADC_L1_SFT 14
361 #define RT5645_M_MONO_ADC_R1 (0x1 << 6)
362 #define RT5645_M_MONO_ADC_R1_SFT 6
377 #define RT5645_M_DAC1_L (0x1 << 14)
378 #define RT5645_M_DAC1_L_SFT 14
393 #define RT5645_M_DAC1_R (0x1 << 6)
394 #define RT5645_M_DAC1_R_SFT 6
397 #define RT5645_M_DAC_L1 (0x1 << 14)
398 #define RT5645_M_DAC_L1_SFT 14
411 #define RT5645_M_DAC_R1 (0x1 << 6)
412 #define RT5645_M_DAC_R1_SFT 6
427 #define RT5645_M_DAC_L1_MONO_L (0x1 << 14)
428 #define RT5645_M_DAC_L1_MONO_L_SFT 14
439 #define RT5645_M_DAC_R1_MONO_R (0x1 << 6)
440 #define RT5645_M_DAC_R1_MONO_R_SFT 6
455 #define RT5645_STO_L_DAC_L_VOL_MASK (0x1 << 14)
456 #define RT5645_STO_L_DAC_L_VOL_SFT 14
471 #define RT5645_DAC_R2_DAC_L_VOL_MASK (0x1 << 6)
472 #define RT5645_DAC_R2_DAC_L_VOL_SFT 6
493 #define RT5645_IF3_DAC_SEL_MASK (0x3 << 6)
494 #define RT5645_IF3_DAC_SEL_SFT 6
503 #define RT5645_M_PDM1_L (0x1 << 14)
504 #define RT5645_M_PDM1_L_SFT 14
518 #define RT5645_PDM1_BUSY (0x1 << 6)
540 #define RT5645_M_MM_L_RM_L (0x1 << 6)
541 #define RT5645_M_MM_L_RM_L_SFT 6
572 #define RT5645_M_MM_R_RM_R (0x1 << 6)
573 #define RT5645_M_MM_R_RM_R_SFT 6
602 #define RT5645_M_DAC1_HM (0x1 << 14)
603 #define RT5645_M_DAC1_HM_SFT 14
609 #define RT5645_G_RM_L_SM_L_MASK (0x3 << 14)
610 #define RT5645_G_RM_L_SM_L_SFT 14
617 #define RT5645_G_OM_L_SM_L_MASK (0x3 << 6)
618 #define RT5645_G_OM_L_SM_L_SFT 6
631 #define RT5645_G_RM_R_SM_R_MASK (0x3 << 14)
632 #define RT5645_G_RM_R_SM_R_SFT 14
639 #define RT5645_G_OM_R_SM_R_MASK (0x3 << 6)
640 #define RT5645_G_OM_R_SM_R_SFT 6
655 #define RT5645_M_DAC_R1_SPM_L (0x1 << 14)
656 #define RT5645_M_DAC_R1_SPM_L_SFT 14
759 #define RT5645_M_DAC_R1_LM (0x1 << 14)
760 #define RT5645_M_DAC_R1_LM_SFT 14
771 #define RT5645_PWR_I2S2 (0x1 << 14)
772 #define RT5645_PWR_I2S2_BIT 14
785 #define RT5645_PWR_DAC_R2 (0x1 << 6)
786 #define RT5645_PWR_DAC_R2_BIT 6
797 #define RT5645_PWR_ADC_MF_L (0x1 << 14)
798 #define RT5645_PWR_ADC_MF_L_BIT 14
811 #define RT5645_PWR_PDM2 (0x1 << 6)
812 #define RT5645_PWR_PDM2_BIT 6
821 #define RT5645_PWR_FV1 (0x1 << 14)
822 #define RT5645_PWR_FV1_BIT 14
833 #define RT5645_PWR_HP_R (0x1 << 6)
834 #define RT5645_PWR_HP_R_BIT 6
847 #define RT5645_PWR_BST2 (0x1 << 14)
848 #define RT5645_PWR_BST2_BIT 14
873 #define RT5645_PWR_OM_R (0x1 << 14)
874 #define RT5645_PWR_OM_R_BIT 14
887 #define RT5645_PWR_HM_R (0x1 << 6)
888 #define RT5645_PWR_HM_R_BIT 6
895 #define RT5645_PWR_SV_R (0x1 << 14)
896 #define RT5645_PWR_SV_R_BIT 14
941 #define RT5645_I2S2_SDI_MASK (0x1 << 6)
942 #define RT5645_I2S2_SDI_SFT 6
943 #define RT5645_I2S2_SDI_I2S1 (0x0 << 6)
944 #define RT5645_I2S2_SDI_I2S2 (0x1 << 6)
999 #define RT5645_DAC_L_OSR_MASK (0x3 << 14)
1000 #define RT5645_DAC_L_OSR_SFT 14
1001 #define RT5645_DAC_L_OSR_128 (0x0 << 14)
1002 #define RT5645_DAC_L_OSR_64 (0x1 << 14)
1003 #define RT5645_DAC_L_OSR_32 (0x2 << 14)
1004 #define RT5645_DAC_L_OSR_16 (0x3 << 14)
1021 #define RT5645_DMIC_2_EN_MASK (0x1 << 14)
1022 #define RT5645_DMIC_2_EN_SFT 14
1023 #define RT5645_DMIC_2_DIS (0x0 << 14)
1024 #define RT5645_DMIC_2_EN (0x1 << 14)
1064 #define RT5645_SCLK_SRC_MASK (0x3 << 14)
1065 #define RT5645_SCLK_SRC_SFT 14
1066 #define RT5645_SCLK_SRC_MCLK (0x0 << 14)
1067 #define RT5645_SCLK_SRC_PLL1 (0x1 << 14)
1068 #define RT5645_SCLK_SRC_RCCLK (0x2 << 14)
1103 #define RT5645_M1_T_MASK (0x1 << 14)
1104 #define RT5645_M1_T_SFT 14
1105 #define RT5645_M1_T_I2S2 (0x0 << 14)
1106 #define RT5645_M1_T_I2S2_D3 (0x1 << 14)
1201 #define RT5645_RSTN_MASK (0x1 << 6)
1202 #define RT5645_RSTN_SFT 6
1203 #define RT5645_RSTN_DIS (0x0 << 6)
1204 #define RT5645_RSTN_EN (0x1 << 6)
1257 #define RT5645_DIG_DP_MASK (0x1 << 6)
1258 #define RT5645_DIG_DP_SFT 6
1259 #define RT5645_DIG_DP_DIS (0x0 << 6)
1260 #define RT5645_DIG_DP_EN (0x1 << 6)
1279 #define RT5645_CP_FQ_96_KHZ 6
1287 #define RT5645_SPK_AG_MASK (0x1 << 14)
1288 #define RT5645_SPK_AG_SFT 14
1289 #define RT5645_SPK_AG_DIS (0x0 << 14)
1290 #define RT5645_SPK_AG_EN (0x1 << 14)
1297 #define RT5645_MIC2_BS_MASK (0x1 << 14)
1298 #define RT5645_MIC2_BS_SFT 14
1299 #define RT5645_MIC2_BS_9AV (0x0 << 14)
1300 #define RT5645_MIC2_BS_75AV (0x1 << 14)
1322 #define RT5645_MIC2_OVTH_MASK (0x3 << 6)
1323 #define RT5645_MIC2_OVTH_SFT 6
1324 #define RT5645_MIC2_OVTH_600UA (0x0 << 6)
1325 #define RT5645_MIC2_OVTH_1500UA (0x1 << 6)
1326 #define RT5645_MIC2_OVTH_2000UA (0x2 << 6)
1351 #define RT5645_EQ_UPD (0x1 << 14)
1352 #define RT5645_EQ_UPD_BIT 14
1373 #define RT5645_EQ_HPF2_MASK (0x1 << 6)
1374 #define RT5645_EQ_HPF2_SFT 6
1375 #define RT5645_EQ_HPF2_DIS (0x0 << 6)
1376 #define RT5645_EQ_HPF2_EN (0x1 << 6)
1414 #define RT5645_DRC_AGC_MASK (0x1 << 14)
1415 #define RT5645_DRC_AGC_SFT 14
1416 #define RT5645_DRC_AGC_DIS (0x0 << 14)
1417 #define RT5645_DRC_AGC_EN (0x1 << 14)
1454 #define RT5645_DRC_AGC_NG_MASK (0x1 << 6)
1455 #define RT5645_DRC_AGC_NG_SFT 6
1456 #define RT5645_DRC_AGC_NG_DIS (0x0 << 6)
1457 #define RT5645_DRC_AGC_NG_EN (0x1 << 6)
1470 #define RT5645_ANC_MASK (0x1 << 14)
1471 #define RT5645_ANC_SFT 14
1472 #define RT5645_ANC_DIS (0x0 << 14)
1473 #define RT5645_ANC_EN (0x1 << 14)
1498 #define RT5645_ANC_SW_MASK (0x1 << 6)
1499 #define RT5645_ANC_SW_SFT 6
1500 #define RT5645_ANC_SW_NOR (0x0 << 6)
1501 #define RT5645_ANC_SW_AUTO (0x1 << 6)
1516 #define RT5645_ANC_CD_MASK (0x1 << 6)
1517 #define RT5645_ANC_CD_SFT 6
1518 #define RT5645_ANC_CD_BOTH (0x0 << 6)
1519 #define RT5645_ANC_CD_IND (0x1 << 6)
1553 #define RT5645_JD_SPR_TRG_MASK (0x1 << 6)
1554 #define RT5645_JD_SPR_TRG_SFT 6
1555 #define RT5645_JD_SPR_TRG_LO (0x0 << 6)
1556 #define RT5645_JD_SPR_TRG_HI (0x1 << 6)
1609 #define RT5645_IRQ_OT_MASK (0x1 << 14)
1610 #define RT5645_IRQ_OT_SFT 14
1611 #define RT5645_IRQ_OT_BP (0x0 << 14)
1612 #define RT5645_IRQ_OT_NOR (0x1 << 14)
1640 #define RT5645_IRQ_MB2_OC_MASK (0x1 << 14)
1641 #define RT5645_IRQ_MB2_OC_SFT 14
1642 #define RT5645_IRQ_MB2_OC_BP (0x0 << 14)
1643 #define RT5645_IRQ_MB2_OC_NOR (0x1 << 14)
1656 #define RT5645_MB2_OC_P_MASK (0x1 << 6)
1657 #define RT5645_MB2_OC_P_SFT 6
1658 #define RT5645_MB2_OC_P_NOR (0x0 << 6)
1659 #define RT5645_MB2_OC_P_INV (0x1 << 6)
1670 #define RT5645_GP2_PIN_MASK (0x1 << 14)
1671 #define RT5645_GP2_PIN_SFT 14
1672 #define RT5645_GP2_PIN_GPIO2 (0x0 << 14)
1673 #define RT5645_GP2_PIN_DMIC1_SCL (0x1 << 14)
1697 #define RT5645_GP6_PIN_MASK (0x1 << 6)
1698 #define RT5645_GP6_PIN_SFT 6
1699 #define RT5645_GP6_PIN_GPIO6 (0x0 << 6)
1700 #define RT5645_GP6_PIN_DMIC2_SDA (0x1 << 6)
1743 #define RT5645_GP3_P_MASK (0x1 << 6)
1744 #define RT5645_GP3_P_SFT 6
1745 #define RT5645_GP3_P_NOR (0x0 << 6)
1746 #define RT5645_GP3_P_INV (0x1 << 6)
1803 #define RT5645_SEQ1_PT_RUN (0x1 << 6)
1804 #define RT5645_SEQ1_PT_RUN_BIT 6
1829 #define RT5645_SCB_MASK (0x1 << 14)
1830 #define RT5645_SCB_SFT 14
1831 #define RT5645_SCB_DIS (0x0 << 14)
1832 #define RT5645_SCB_EN (0x1 << 14)
1851 #define RT5645_M_BB_HPF_R_MASK (0x1 << 6)
1852 #define RT5645_M_BB_HPF_R_SFT 6
1860 #define RT5645_M_MP3_R_MASK (0x1 << 14)
1861 #define RT5645_M_MP3_R_SFT 14
1872 #define RT5645_M_MP3_ORG_L_MASK (0x1 << 6)
1873 #define RT5645_M_MP3_ORG_L_SFT 6
1892 #define RT5645_3D_HP_MASK (0x1 << 14)
1893 #define RT5645_3D_HP_SFT 14
1894 #define RT5645_3D_HP_DIS (0x0 << 14)
1895 #define RT5645_3D_HP_EN (0x1 << 14)
1912 #define RT5645_M_3D_REVB_MASK (0x1 << 6)
1913 #define RT5645_M_3D_REVB_SFT 6
1928 #define RT5645_ZD_T_MASK (0x3 << 6)
1929 #define RT5645_ZD_T_SFT 6
1950 #define RT5645_HPD_RCV_MASK (0x7 << 6)
1951 #define RT5645_HPD_RCV_SFT 6
1979 #define RT5645_SPO_SV_MASK (0x1 << 14)
1980 #define RT5645_SPO_SV_SFT 14
1981 #define RT5645_SPO_SV_DIS (0x0 << 14)
1982 #define RT5645_SPO_SV_EN (0x1 << 14)
2004 #define RT5645_M_ZCD_SM_R (0x1 << 6)
2019 #define RT5645_DA1_ZDET_SFT 6
2046 #define RT5645_HPF_FC_MASK (0x3f << 6)
2047 #define RT5645_HPF_FC_SFT 6
2060 #define RT5645_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2062 #define RT5645_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2071 #define RT5645_DP_ATT_MASK (0x3 << 14)
2072 #define RT5645_DP_ATT_SFT 14
2089 #define RT5645_JD_CBJ_POL (0x1 << 6)