2  * rk3308_codec.h -- RK3308 ALSA Soc Audio Driver
77 #define ACODEC_DAC_HPDET_STATUS			0x38 /* REG 0x0e, Read-only */
83 #define ACODEC_S_DAC_HPDET_STATUS		0x34 /* REG 0x0d, Read-only */
134 #define RK3308_ADC_DIG_OFFSET(ch)		((ch & 0x3) * 0xc0 + 0x0)  argument
136 #define RK3308_ADC_DIG_CON01(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_I2S_CTL0)  argument
137 #define RK3308_ADC_DIG_CON02(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_I2S_CTL1)  argument
138 #define RK3308_ADC_DIG_CON03(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_BIST_MODE_SEL)  argument
139 #define RK3308_ADC_DIG_CON04(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_HPF_PATH)  argument
140 #define RK3308BS_ADC_DIG_CON05(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_S_ADC_DIG_VOL_CON_L)  argument
141 #define RK3308BS_ADC_DIG_CON06(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_S_ADC_DIG_VOL_CON_R)  argument
142 #define RK3308_ADC_DIG_CON07(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_DATA_PATH) /* Removed fro…  argument
144 #define RK3308_ALC_L_DIG_CON00(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL0)  argument
145 #define RK3308_ALC_L_DIG_CON01(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL1)  argument
146 #define RK3308_ALC_L_DIG_CON02(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL2)  argument
147 #define RK3308_ALC_L_DIG_CON03(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL3)  argument
148 #define RK3308_ALC_L_DIG_CON04(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL4)  argument
149 #define RK3308_ALC_L_DIG_CON05(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_LO_MAX)  argument
150 #define RK3308_ALC_L_DIG_CON06(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_HI_MAX)  argument
151 #define RK3308_ALC_L_DIG_CON07(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_LO_MIN)  argument
152 #define RK3308_ALC_L_DIG_CON08(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_HI_MIN)  argument
153 #define RK3308_ALC_L_DIG_CON09(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL5)  argument
154 #define RK3308BS_ALC_L_DIG_CON11(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_S_ADC_PEAK_DET_VALUE_DEC_…  argument
155 #define RK3308_ALC_L_DIG_CON12(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_AGC_L_RO_GAIN)  argument
157 #define RK3308_ALC_R_DIG_CON00(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_CTL0)  argument
158 #define RK3308_ALC_R_DIG_CON01(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_CTL1)  argument
159 #define RK3308_ALC_R_DIG_CON02(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_CTL2)  argument
160 #define RK3308_ALC_R_DIG_CON03(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_CTL3)  argument
161 #define RK3308_ALC_R_DIG_CON04(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_CTL4)  argument
162 #define RK3308_ALC_R_DIG_CON05(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_LO_MAX)  argument
163 #define RK3308_ALC_R_DIG_CON06(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_HI_MAX)  argument
164 #define RK3308_ALC_R_DIG_CON07(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_LO_MIN)  argument
165 #define RK3308_ALC_R_DIG_CON08(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_HI_MIN)  argument
166 #define RK3308_ALC_R_DIG_CON09(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_CTL5)  argument
167 #define RK3308BS_ALC_R_DIG_CON11(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_S_ADC_PEAK_DET_VALUE_DEC_…  argument
168 #define RK3308_ALC_R_DIG_CON12(ch)		(RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_AGC_R_RO_GAIN)  argument
206 #define RK3308_ADC_ANA_OFFSET(ch)		(((ch) & 0x3) * 0x40 + 0x340)  argument
208 #define RK3308_ADC_ANA_CON00(ch)		(RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_MIC_CTL)  argument
209 #define RK3308_ADC_ANA_CON01(ch)		(RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_MIC_GAIN)  argument
210 #define RK3308_ADC_ANA_CON02(ch)		(RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_ALC_CTL)  argument
211 #define RK3308_ADC_ANA_CON03(ch)		(RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_ALC_GAIN1)  argument
212 #define RK3308_ADC_ANA_CON04(ch)		(RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_ALC_GAIN2)  argument
213 #define RK3308_ADC_ANA_CON05(ch)		(RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_CTL0)  argument
214 #define RK3308_ADC_ANA_CON06(ch)		(RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_CTL1)  argument
215 #define RK3308_ADC_ANA_CON07(ch)		(RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_CTL2)  argument
216 #define RK3308_ADC_ANA_CON08(ch)		(RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_CTL3)  argument
217 #define RK3308BS_ADC_ANA_CON09(ch)		(RK3308_ADC_ANA_OFFSET(ch) + ACODEC_S_ADC_ANA_CTL4)  argument
218 #define RK3308_ADC_ANA_CON10(ch)		(RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_CTL5)  argument
219 #define RK3308_ADC_ANA_CON11(ch)		(RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_ALC_PGA)  argument
241 /* RK3308_GLB_CON - REG: 0x0000 */
249 #define RK3308_DAC_MCLK_MSK			(1 << 4)
250 #define RK3308_DAC_MCLK_DIS			(1 << 4)
251 #define RK3308_DAC_MCLK_EN			(0 << 4)
260 /* RK3308_ADC_DIG_CON01 - REG: 0x0004 */
288 /* RK3308_ADC_DIG_CON02 - REG: 0x0008 */
292 #define RK3308_ADC_MODE_MSK			(1 << 4)
293 #define RK3308_ADC_MODE_MASTER			(1 << 4)
294 #define RK3308_ADC_MODE_SLAVE			(0 << 4)
308 /* RK3308_ADC_DIG_CON03 - REG: 0x000c */
322 /* RK3308_ADC_DIG_CON04 - REG: 0x0010 */
333 /* RK3308BS_ADC_DIG_CON05 - REG: 0x0014 */
336 /* RK3308BS_ADC_DIG_CON06 - REG: 0x0018 */
341 /* RK3308_ADC_DIG_CON07 - REG: 0x001c */
342 #define RK3308_ADCL_DATA_SFT			4
352  * RK3308_ALC_L_DIG_CON00 - REG: 0x0040 + ch * 0xc0
353  * RK3308_ALC_R_DIG_CON00 - REG: 0x0080 + ch * 0xc0
357 #define RK3308_CTRL_GEN_SFT			4
378  * RK3308_ALC_L_DIG_CON01 - REG: 0x0044 + ch * 0xc0
379  * RK3308_ALC_R_DIG_CON01 - REG: 0x0084 + ch * 0xc0
381 #define RK3308_AGC_DECAY_TIME_SFT		4
438  * RK3308_ALC_L_DIG_CON02 - REG: 0x0048 + ch * 0xc0
439  * RK3308_ALC_R_DIG_CON02 - REG: 0x0088 + ch * 0xc0
447 #define RK3308_AGC_FAST_DEC_EN			(0x1 << 4)
448 #define RK3308_AGC_FAST_DEC_DIS			(0x0 << 4)
463  * RK3308_ALC_L_DIG_CON03 - REG: 0x004c + ch * 0xc0
464  * RK3308_ALC_R_DIG_CON03 - REG: 0x008c + ch * 0xc0
506  * RK3308_ALC_L_DIG_CON04 - REG: 0x0050 + ch * 0xc0
507  * RK3308_ALC_R_DIG_CON04 - REG: 0x0090 + ch * 0xc0
523  * RK3308_ALC_L_DIG_CON05 - REG: 0x0054 + ch * 0xc0
524  * RK3308_ALC_R_DIG_CON05 - REG: 0x0094 + ch * 0xc0
529  * RK3308_ALC_L_DIG_CON06 - REG: 0x0058 + ch * 0xc0
530  * RK3308_ALC_R_DIG_CON06 - REG: 0x0098 + ch * 0xc0
535  * RK3308_ALC_L_DIG_CON07 - REG: 0x005c + ch * 0xc0
536  * RK3308_ALC_R_DIG_CON07 - REG: 0x009c + ch * 0xc0
541  * RK3308_ALC_L_DIG_CON08 - REG: 0x0060 + ch * 0xc0
542  * RK3308_ALC_R_DIG_CON08 - REG: 0x00a0 + ch * 0xc0
547  * RK3308_ALC_L_DIG_CON09 - REG: 0x0064 + ch * 0xc0
548  * RK3308_ALC_R_DIG_CON09 - REG: 0x00a4 + ch * 0xc0
579  * RK3308BS_ALC_L_DIG_CON11 - REG: 0x006c + ch * 0xc0
580  * RK3308BS_ALC_R_DIG_CON11 - REG: 0x00ac + ch * 0xc0
585  * RK3308_ALC_L_DIG_CON12 - REG: 0x0070 + ch * 0xc0
586  * RK3308_ALC_R_DIG_CON12 - REG: 0x00b0 + ch * 0xc0
591  * RK3308BS_ALC_L_DIG_CON12 - REG: 0x0070 + ch * 0xc0
592  * RK3308BS_ALC_R_DIG_CON12 - REG: 0x00b0 + ch * 0xc0
596  * RK3308BS_ALC_L_DIG_CON13 - REG: 0x0074 + ch * 0xc0
597  * RK3308BS_ALC_R_DIG_CON13 - REG: 0x00b4 + ch * 0xc0
601  * RK3308BS_ALC_L_DIG_CON14 - REG: 0x0078 + ch * 0xc0
602  * RK3308BS_ALC_R_DIG_CON14 - REG: 0x00b8 + ch * 0xc0
606 /* RK3308_DAC_DIG_CON01 - REG: 0x0304 */
629 /* RK3308_DAC_DIG_CON02 - REG: 0x0308 */
639 #define RK3308_DAC_MODE_MSK			(0x1 << 4)
640 #define RK3308_DAC_MODE_MASTER			(0x1 << 4)
641 #define RK3308_DAC_MODE_SLAVE			(0x0 << 4)
655 /* RK3308_DAC_DIG_CON03 - REG: 0x030C */
669 /* RK3308_DAC_DIG_CON04 - REG: 0x0310 */
670 #define RK3308_DAC_MODULATOR_GAIN_SFT		4
681 /* RK3308BS_DAC_DIG_CON04 - REG: 0x0310 */
687 /* RK3308_DAC_DIG_CON05 - REG: 0x0314 */
693 /* RK3308BS_DAC_DIG_CON05 - REG: 0x0314 */
699 /* RK3308_DAC_DIG_CON10 - REG: 0x0328 */
702 /* RK3308_DAC_DIG_CON11 - REG: 0x032c */
705 /* RK3308BS_DAC_DIG_CON09 - REG: 0x0324 */
708 /* RK3308BS_DAC_DIG_CON10 - REG: 0x0328 */
711 /* RK3308BS_DAC_DIG_CON11 - REG: 0x032c */
714 /* RK3308BS_DAC_DIG_CON12 - REG: 0x0330 */
717 /* RK3308_ADC_ANA_CON00 - REG: 0x0340 */
726 #define RK3308_ADC_CH2_BUF_REF_EN		(0x1 << 4)
727 #define RK3308_ADC_CH2_BUF_REF_DIS		(0x0 << 4)
737 /* RK3308_ADC_ANA_CON01 - REG: 0x0344
739  * The PGA of MIC-INs:
740  * 0x0 - MIC1~MIC8 0dB
741  * 0x1 - MIC1~MIC8 6.6dB
742  * 0x2 - MIC1~MIC8 13dB
743  * 0x3 - MIC1~MIC8 20dB
747 #define RK3308_ADC_CH2_MIC_GAIN_SFT		4
763 /* RK3308_ADC_ANA_CON02 - REG: 0x0348 */
764 #define RK3308_ADC_CH2_ALC_ZC_MSK		(0x7 << 4)
769 #define RK3308_ADC_CH2_ALC_EN			(0x1 << 4)
770 #define RK3308_ADC_CH2_ALC_DIS			(0x0 << 4)
780 /* RK3308_ADC_ANA_CON03 - REG: 0x034c */
818 /* RK3308_ADC_ANA_CON04 - REG: 0x0350 */
856 /* RK3308_ADC_ANA_CON05 - REG: 0x0354 */
857 #define RK3308_ADC_CH2_ADC_CLK_MSK		(0x7 << 4)
862 #define RK3308_ADC_CH2_CLK_EN			(0x1 << 4)
863 #define RK3308_ADC_CH2_CLK_DIS			(0x0 << 4)
873 /* RK3308_ADC_ANA_CON06 - REG: 0x0358 */
878 /* RK3308_ADC_ANA_CON07 - REG: 0x035c */
887 #define RK3308_ADC_CH1_IN_SEL_SFT		4
913 /* RK3308_ADC_ANA_CON08 - REG: 0x0360 */
914 #define RK3308_ADC_MICBIAS_CURRENT_MSK		(0x1 << 4)
915 #define RK3308_ADC_MICBIAS_CURRENT_EN		(0x1 << 4)
916 #define RK3308_ADC_MICBIAS_CURRENT_DIS		(0x0 << 4)
919 /* RK3308BS_ADC_ANA_CON09 - REG: 0x0364 */
920 #define RK3308BS_ADC_MICBIAS_OPA_VBIAS(x)	(((x) & 0x7) << 4)
924 /* RK3308_ADC_ANA_CON10 - REG: 0x0368 */
935 /* RK3308_ADC_ANA_CON11 - REG: 0x036c */
943 /* RK3308_DAC_ANA_CON00 - REG: 0x0440 */
944 #define RK3308_DAC_CURRENT_SEL_SFT		4
954 /* RK3308_DAC_ANA_CON01 - REG: 0x0444 */
958 #define RK3308_DAC_HPOUT_POP_SOUND_R_SFT	4
972 /* RK3308_DAC_ANA_CON02 - REG: 0x0448 */
979 #define RK3308_DAC_R_REF_EN			(0x1 << 4)
980 #define RK3308_DAC_R_REF_DIS			(0x0 << 4)
990 /* RK3308_DAC_ANA_CON03 - REG: 0x044c */
995 #define RK3308_DAC_R_HPOUT_UNMUTE		(0x1 << 4)
996 #define RK3308_DAC_R_HPOUT_MUTE			(0x0 << 4)
1004 /* RK3308_DAC_ANA_CON04 - REG: 0x0450 */
1014 #define RK3308_DAC_R_LINEOUT_EN			(0x1 << 4)
1015 #define RK3308_DAC_R_LINEOUT_DIS		(0x0 << 4)
1028 /* RK3308_DAC_ANA_CON05 - REG: 0x0454, step is 1.5db */
1064 /* RK3308_DAC_ANA_CON06 - REG: 0x0458, step is 1.5db */
1100 /* RK3308_DAC_ANA_CON07 - REG: 0x045c */
1101 #define RK3308_DAC_R_HPOUT_DRV_SFT		4
1108 /* RK3308_DAC_ANA_CON08 - REG: 0x0460 */
1109 #define RK3308_DAC_R_LINEOUT_DRV_SFT		4
1116 /* RK3308_DAC_ANA_CON12 - REG: 0x0470 */
1125 #define RK3308_DAC_R_HPMIX_GAIN_SFT		4
1142 /* RK3308_DAC_ANA_CON13 - REG: 0x0474 */
1147 #define RK3308_DAC_R_HPMIX_EN			(0x1 << 4)
1148 #define RK3308_DAC_R_HPMIX_DIS			(0x0 << 4)
1156 /* RK3308_DAC_ANA_CON14 - REG: 0x0478 */
1157 #define RK3308_DAC_VCM_LINEOUT_EN		(0x1 << 4)
1158 #define RK3308_DAC_VCM_LINEOUT_DIS		(0x0 << 4)
1168 /* RK3308_DAC_ANA_CON15 - REG: 0x047C */
1169 #define RK3308_DAC_LINEOUT_POP_SOUND_R_SFT	4