soc/codecs/es8328.c

1 // SPDX-License-Identifier: GPL-2.0-only
3  * es8328.c  --  ES8328 ALSA SoC Audio driver
5  * Copyright 2014 Sutajio Ko-Usagi PTE LTD
10 #include <linux/clk.h>
91 	struct clk *clk;  member
110 static const DECLARE_TLV_DB_SCALE(play_tlv, -3000, 100, 0);
111 static const DECLARE_TLV_DB_SCALE(dac_adc_tlv, -9600, 50, 0);
112 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
134 	if (es8328->deemph) {  in es8328_set_deemph()
137 			if (abs(deemph_settings[i].rate - es8328->playback_fs) <  in es8328_set_deemph()
138 			    abs(deemph_settings[best].rate - es8328->playback_fs))  in es8328_set_deemph()
147 	dev_dbg(component->dev, "Set deemphasis %d\n", val);  in es8328_set_deemph()
159 	ucontrol->value.integer.value[0] = es8328->deemph;  in es8328_get_deemph()
168 	unsigned int deemph = ucontrol->value.integer.value[0];  in es8328_put_deemph()
172 		return -EINVAL;  in es8328_put_deemph()
174 	if (es8328->deemph == deemph)  in es8328_put_deemph()
181 	es8328->deemph = deemph;  in es8328_put_deemph()
287 /* Mono ADC Mux */
298 	SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
300 	SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
315 	SND_SOC_DAPM_ADC("Right ADC", "Right Capture", ES8328_ADCPOWER,
317 	SND_SOC_DAPM_ADC("Left ADC", "Left Capture", ES8328_ADCPOWER,
327 	SND_SOC_DAPM_SUPPLY("ADC STM", ES8328_CHIPPOWER,
332 	SND_SOC_DAPM_SUPPLY("ADC DIG", ES8328_CHIPPOWER,
337 	SND_SOC_DAPM_SUPPLY("ADC DLL", ES8328_CHIPPOWER,
340 	SND_SOC_DAPM_SUPPLY("ADC Vref", ES8328_CHIPPOWER,
402 	{ "Left ADC Mux", "Stereo", "Left PGA Mux" },
403 	{ "Left ADC Mux", "Mono (Left)", "Left PGA Mux" },
404 	{ "Left ADC Mux", "Digital Mono", "Left PGA Mux" },
406 	{ "Right ADC Mux", "Stereo", "Right PGA Mux" },
407 	{ "Right ADC Mux", "Mono (Right)", "Right PGA Mux" },
408 	{ "Right ADC Mux", "Digital Mono", "Right PGA Mux" },
410 	{ "Left ADC", NULL, "Left ADC Mux" },
411 	{ "Right ADC", NULL, "Right ADC Mux" },
413 	{ "ADC DIG", NULL, "ADC STM" },
414 	{ "ADC DIG", NULL, "ADC Vref" },
415 	{ "ADC DIG", NULL, "ADC DLL" },
417 	{ "Left ADC", NULL, "ADC DIG" },
418 	{ "Right ADC", NULL, "ADC DIG" },
467 	return snd_soc_component_update_bits(dai->component, ES8328_DACCONTROL3,  in es8328_mute()
475 	struct snd_soc_component *component = dai->component;  in es8328_startup()
478 	if (es8328->master && es8328->sysclk_constraints)  in es8328_startup()
479 		snd_pcm_hw_constraint_list(substream->runtime, 0,  in es8328_startup()
481 				es8328->sysclk_constraints);  in es8328_startup()
490 	struct snd_soc_component *component = dai->component;  in es8328_hw_params()
497 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)  in es8328_hw_params()
502 	if (es8328->master) {  in es8328_hw_params()
503 		if (!es8328->sysclk_constraints) {  in es8328_hw_params()
504 			dev_err(component->dev, "No MCLK configured\n");  in es8328_hw_params()
505 			return -EINVAL;  in es8328_hw_params()
508 		for (i = 0; i < es8328->sysclk_constraints->count; i++)  in es8328_hw_params()
509 			if (es8328->sysclk_constraints->list[i] ==  in es8328_hw_params()
513 		if (i == es8328->sysclk_constraints->count) {  in es8328_hw_params()
514 			dev_err(component->dev,  in es8328_hw_params()
517 			return -EINVAL;  in es8328_hw_params()
519 		ratio = es8328->mclk_ratios[i];  in es8328_hw_params()
522 		es8328->mclkdiv2 = 0;  in es8328_hw_params()
527 			es8328->mclkdiv2 ? ES8328_MASTERMODE_MCLKDIV2 : 0);  in es8328_hw_params()
546 		return -EINVAL;  in es8328_hw_params()
549 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {  in es8328_hw_params()
554 		es8328->playback_fs = params_rate(params);  in es8328_hw_params()
567 	struct snd_soc_component *component = codec_dai->component;  in es8328_set_sysclk()
573 		es8328->sysclk_constraints = NULL;  in es8328_set_sysclk()
574 		es8328->mclk_ratios = NULL;  in es8328_set_sysclk()
580 		es8328->sysclk_constraints = &constraints_11289;  in es8328_set_sysclk()
581 		es8328->mclk_ratios = ratios_11289;  in es8328_set_sysclk()
587 		es8328->sysclk_constraints = &constraints_12288;  in es8328_set_sysclk()
588 		es8328->mclk_ratios = ratios_12288;  in es8328_set_sysclk()
595 		es8328->sysclk_constraints = &constraints_12000;  in es8328_set_sysclk()
596 		es8328->mclk_ratios = ratios_12000;  in es8328_set_sysclk()
599 		return -EINVAL;  in es8328_set_sysclk()
602 	es8328->mclkdiv2 = mclkdiv2;  in es8328_set_sysclk()
609 	struct snd_soc_component *component = codec_dai->component;  in es8328_set_dai_fmt()
620 		es8328->master = true;  in es8328_set_dai_fmt()
626 		es8328->master = false;  in es8328_set_dai_fmt()
629 		return -EINVAL;  in es8328_set_dai_fmt()
647 		return -EINVAL;  in es8328_set_dai_fmt()
652 		return -EINVAL;  in es8328_set_dai_fmt()
723 	.name = "es8328-hifi-analog",
749 	clk_disable_unprepare(es8328->clk);  in es8328_suspend()
751 	ret = regulator_bulk_disable(ARRAY_SIZE(es8328->supplies),  in es8328_suspend()
752 			es8328->supplies);  in es8328_suspend()
754 		dev_err(component->dev, "unable to disable regulators\n");  in es8328_suspend()
762 	struct regmap *regmap = dev_get_regmap(component->dev, NULL);  in es8328_resume()
768 	ret = clk_prepare_enable(es8328->clk);  in es8328_resume()
770 		dev_err(component->dev, "unable to enable clock\n");  in es8328_resume()
774 	ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies),  in es8328_resume()
775 					es8328->supplies);  in es8328_resume()
777 		dev_err(component->dev, "unable to enable regulators\n");  in es8328_resume()
784 		dev_err(component->dev, "unable to sync regcache\n");  in es8328_resume()
798 	ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies),  in es8328_component_probe()
799 					es8328->supplies);  in es8328_component_probe()
801 		dev_err(component->dev, "unable to enable regulators\n");  in es8328_component_probe()
806 	es8328->clk = devm_clk_get(component->dev, NULL);  in es8328_component_probe()
807 	if (IS_ERR(es8328->clk)) {  in es8328_component_probe()
808 		dev_err(component->dev, "codec clock missing or invalid\n");  in es8328_component_probe()
809 		ret = PTR_ERR(es8328->clk);  in es8328_component_probe()
813 	ret = clk_prepare_enable(es8328->clk);  in es8328_component_probe()
815 		dev_err(component->dev, "unable to prepare codec clk\n");  in es8328_component_probe()
822 	regulator_bulk_disable(ARRAY_SIZE(es8328->supplies),  in es8328_component_probe()
823 			       es8328->supplies);  in es8328_component_probe()
833 	if (es8328->clk)  in es8328_remove()
834 		clk_disable_unprepare(es8328->clk);  in es8328_remove()
836 	regulator_bulk_disable(ARRAY_SIZE(es8328->supplies),  in es8328_remove()
837 			       es8328->supplies);  in es8328_remove()
880 		return -ENOMEM;  in es8328_probe()
882 	es8328->regmap = regmap;  in es8328_probe()
884 	for (i = 0; i < ARRAY_SIZE(es8328->supplies); i++)  in es8328_probe()
885 		es8328->supplies[i].supply = supply_names[i];  in es8328_probe()
887 	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(es8328->supplies),  in es8328_probe()
888 				es8328->supplies);  in es8328_probe()