soc/codecs/cx20810_config.h

39 	0x78, 0x2D, /* Enable VREF @ 2.8V (5V) or 2.6V (3.3V) */
40 	0x78, 0x2D, /* Enable VREF @ 2.8V (5V) or 2.6V (3.3V) */
41 	0x78, 0x2D, /* Enable VREF @ 2.8V (5V) or 2.6V (3.3V) */
42 	0x78, 0x2D, /* Enable VREF @ 2.8V (5V) or 2.6V (3.3V) */
43 	0x78, 0x2D, /* Enable VREF @ 2.8V (5V) or 2.6V (3.3V) */
44 	0x78, 0x2D, /* Enable VREF @ 2.8V (5V) or 2.6V (3.3V) */
45 	0x78, 0x6D, /* Enable Analog LDO */
46 	0x78, 0x6D, /* Enable Analog LDO */
47 	0x78, 0x6D, /* Enable Analog LDO */
48 	0x78, 0x6D, /* Enable Analog LDO */
49 	0x78, 0x6D, /* Enable Analog LDO */
50 	0x78, 0x6D, /* Enable Analog LDO */
51 	0x7A, 0x01, /* Enable VREFP */
55 	0x0c, 0x3B, /* Enable I2S-TX and set Master Mode, enable ADC3/4 FIFO */
58 	0x30, 0x14, /* 7 wire mode,24-bit sample size,// Normal mode */
59 	0x31, 0x07, /* Set 64 cycle per frame TX */
60 	0x33, 0x1F, /*  TX WS ,32 cycle */
61 	0x35, 0xA8, /* Lj 1bit delay,  enable TX1,2 */
63 	0x0A, 0x03, /* Set TX divisor is Source Clock / 4 (Bclk,3.072Mhz) */
64 	0x0A, 0x83, /* Enable divisor */
79 	0x10, 0x1F, /* Enable all ADC clocks and ADC digital */
80 	0x11, 0x4F, /* Enable all ADCs and set 48kHz sample rate */
81 	0x10, 0x5F, /* Enable all ADC clocks, ADC digital and ADC Mic Clock Gate */
84 	 *0xA0 , 0x0F ,// ADC1, Mute PGA, enable AAF/ADC/PGA
85 	 *0xA7 , 0x0F ,// ADC2, Mute PGA, enable AAF/ADC/PGA
86 	 *0xAE , 0x0F ,// ADC3, Mute PGA, enable AAF/ADC/PGA
87 	 *0xB5 , 0x0F ,// ADC4, Mute PGA, enable AAF/ADC/PGA
133 	0x35, 0xAC, /* TX right justified and revert i2s1+i2s2 */
161 	/* enable MCLK to chip */
169 	0x10, 0x1F,  /* Enable all ADC clocks and ADC digital */
170 	0x11, 0x4F,  /* Enable all ADC and set 48k sample rate */
171 	0x10, 0x5F,  /* Enable all ADC clocks,
214 	0x35, 0xAC, /* TX right justified and revert i2s1+i2s2 */
237 	0x09, 0x40, /*  I2S TX Bit Clock */
251 	/* enable PLL1 */
273 	/* enable MCLK to chip */
280 	0x10, 0x1F, /* Enable all ADC clocks and ADC digital */
281 	0x11, 0x4F, /* Enable all ADC and set 48k sample rate */
282 	0x10, 0x5F, /* Enable all ADC clocks,
311 	0x0C, 0x0A, /*  RT clock disable, TX clock enable,
312 					enable clock to ADC3/4 */
315 	/* Tx sample size:16bit, Normal mode */
317 	0x30, 0x14, /*  Tx sample size:24bit, Normal mode */
318 	0x35, 0xA2, /*  left justified, enable I2S-1 and I2S-2 */
348 	 *  [1] enable [3] mute [7] bypass */
378 	0x0C, 0x0A, /* RT clock disable, TX clock enable,
379 		       enable clock to ADC3/4 */
382 	/*  Tx sample size:16bit, Normal mode */
384 	0x30, 0x14, /*  Tx sample size:24bit, Normal mode */
385 	0x35, 0xA2, /*  left justified, enable I2S-1 and I2S-2 */
420 	0x0C, 0x0A,/* RT clock disable, TX clock enable,
421 		      enable clock to ADC3/4 */
424 	/* Tx sample size:16bit, Normal mode */
426 	0x30, 0x14,/* Tx sample size:24bit, Normal mode */
427 	0x35, 0xA2,/* left justified, enable I2S-1 and I2S-2 */
461 	0x0C, 0x0A,/* RT clock disable, TX clock enable,
462 		      enable clock to ADC3/4 */
465 	0x30, 0x0A,/*  Tx sample size:16bit, Normal mode */
466 	/* Tx sample size:24bit, Normal mode */
468 	0x35, 0xA2,/*  left justified, enable I2S-1 and I2S-2 */
502 	0x0C, 0x0A,/* RT clock disable, TX clock enable,
503 		      enable clock to ADC3/4 */
506 	0x30, 0x0A,/* Tx sample size:16bit, Normal mode */
507 	/* Tx sample size:24bit, Normal mode */
509 	0x35, 0xA2,/* left justified, enable I2S-1 and I2S-2 */