30 #define INTH_R5F_STATUS_OFFSET     0x040
31 #define INTH_R5F_CLEAR_OFFSET      0x048
32 #define INTH_R5F_MASK_SET_OFFSET   0x050
33 #define INTH_R5F_MASK_CLEAR_OFFSET 0x054
35 #define BF_REARM_FREE_MARK_OFFSET 0x344
36 #define BF_REARM_FULL_MARK_OFFSET 0x348
40 #define SRC_RBUF_0_RDADDR_OFFSET 0x500
41 #define SRC_RBUF_1_RDADDR_OFFSET 0x518
42 #define SRC_RBUF_2_RDADDR_OFFSET 0x530
43 #define SRC_RBUF_3_RDADDR_OFFSET 0x548
44 #define SRC_RBUF_4_RDADDR_OFFSET 0x560
45 #define SRC_RBUF_5_RDADDR_OFFSET 0x578
46 #define SRC_RBUF_6_RDADDR_OFFSET 0x590
49 #define SRC_RBUF_0_WRADDR_OFFSET 0x504
50 #define SRC_RBUF_1_WRADDR_OFFSET 0x51c
51 #define SRC_RBUF_2_WRADDR_OFFSET 0x534
52 #define SRC_RBUF_3_WRADDR_OFFSET 0x54c
53 #define SRC_RBUF_4_WRADDR_OFFSET 0x564
54 #define SRC_RBUF_5_WRADDR_OFFSET 0x57c
55 #define SRC_RBUF_6_WRADDR_OFFSET 0x594
58 #define SRC_RBUF_0_BASEADDR_OFFSET 0x508
59 #define SRC_RBUF_1_BASEADDR_OFFSET 0x520
60 #define SRC_RBUF_2_BASEADDR_OFFSET 0x538
61 #define SRC_RBUF_3_BASEADDR_OFFSET 0x550
62 #define SRC_RBUF_4_BASEADDR_OFFSET 0x568
63 #define SRC_RBUF_5_BASEADDR_OFFSET 0x580
64 #define SRC_RBUF_6_BASEADDR_OFFSET 0x598
67 #define SRC_RBUF_0_ENDADDR_OFFSET 0x50c
68 #define SRC_RBUF_1_ENDADDR_OFFSET 0x524
69 #define SRC_RBUF_2_ENDADDR_OFFSET 0x53c
70 #define SRC_RBUF_3_ENDADDR_OFFSET 0x554
71 #define SRC_RBUF_4_ENDADDR_OFFSET 0x56c
72 #define SRC_RBUF_5_ENDADDR_OFFSET 0x584
73 #define SRC_RBUF_6_ENDADDR_OFFSET 0x59c
76 #define SRC_RBUF_0_FREE_MARK_OFFSET 0x510
77 #define SRC_RBUF_1_FREE_MARK_OFFSET 0x528
78 #define SRC_RBUF_2_FREE_MARK_OFFSET 0x540
79 #define SRC_RBUF_3_FREE_MARK_OFFSET 0x558
80 #define SRC_RBUF_4_FREE_MARK_OFFSET 0x570
81 #define SRC_RBUF_5_FREE_MARK_OFFSET 0x588
82 #define SRC_RBUF_6_FREE_MARK_OFFSET 0x5a0
85 #define DST_RBUF_0_RDADDR_OFFSET 0x5c0
86 #define DST_RBUF_1_RDADDR_OFFSET 0x5d8
87 #define DST_RBUF_2_RDADDR_OFFSET 0x5f0
88 #define DST_RBUF_3_RDADDR_OFFSET 0x608
89 #define DST_RBUF_4_RDADDR_OFFSET 0x620
90 #define DST_RBUF_5_RDADDR_OFFSET 0x638
93 #define DST_RBUF_0_WRADDR_OFFSET 0x5c4
94 #define DST_RBUF_1_WRADDR_OFFSET 0x5dc
95 #define DST_RBUF_2_WRADDR_OFFSET 0x5f4
96 #define DST_RBUF_3_WRADDR_OFFSET 0x60c
97 #define DST_RBUF_4_WRADDR_OFFSET 0x624
98 #define DST_RBUF_5_WRADDR_OFFSET 0x63c
101 #define DST_RBUF_0_BASEADDR_OFFSET 0x5c8
102 #define DST_RBUF_1_BASEADDR_OFFSET 0x5e0
103 #define DST_RBUF_2_BASEADDR_OFFSET 0x5f8
104 #define DST_RBUF_3_BASEADDR_OFFSET 0x610
105 #define DST_RBUF_4_BASEADDR_OFFSET 0x628
106 #define DST_RBUF_5_BASEADDR_OFFSET 0x640
109 #define DST_RBUF_0_ENDADDR_OFFSET 0x5cc
110 #define DST_RBUF_1_ENDADDR_OFFSET 0x5e4
111 #define DST_RBUF_2_ENDADDR_OFFSET 0x5fc
112 #define DST_RBUF_3_ENDADDR_OFFSET 0x614
113 #define DST_RBUF_4_ENDADDR_OFFSET 0x62c
114 #define DST_RBUF_5_ENDADDR_OFFSET 0x644
117 #define DST_RBUF_0_FULL_MARK_OFFSET 0x5d0
118 #define DST_RBUF_1_FULL_MARK_OFFSET 0x5e8
119 #define DST_RBUF_2_FULL_MARK_OFFSET 0x600
120 #define DST_RBUF_3_FULL_MARK_OFFSET 0x618
121 #define DST_RBUF_4_FULL_MARK_OFFSET 0x630
122 #define DST_RBUF_5_FULL_MARK_OFFSET 0x648
127 #define ESR0_STATUS_OFFSET 0x900
128 #define ESR1_STATUS_OFFSET 0x918
129 #define ESR2_STATUS_OFFSET 0x930
130 #define ESR3_STATUS_OFFSET 0x948
131 #define ESR4_STATUS_OFFSET 0x960
134 #define ESR0_STATUS_CLR_OFFSET 0x908
135 #define ESR1_STATUS_CLR_OFFSET 0x920
136 #define ESR2_STATUS_CLR_OFFSET 0x938
137 #define ESR3_STATUS_CLR_OFFSET 0x950
138 #define ESR4_STATUS_CLR_OFFSET 0x968
141 #define ESR0_MASK_STATUS_OFFSET 0x90c
142 #define ESR1_MASK_STATUS_OFFSET 0x924
143 #define ESR2_MASK_STATUS_OFFSET 0x93c
144 #define ESR3_MASK_STATUS_OFFSET 0x954
145 #define ESR4_MASK_STATUS_OFFSET 0x96c
148 #define ESR0_MASK_SET_OFFSET 0x910
149 #define ESR1_MASK_SET_OFFSET 0x928
150 #define ESR2_MASK_SET_OFFSET 0x940
151 #define ESR3_MASK_SET_OFFSET 0x958
152 #define ESR4_MASK_SET_OFFSET 0x970
155 #define ESR0_MASK_CLR_OFFSET 0x914
156 #define ESR1_MASK_CLR_OFFSET 0x92c
157 #define ESR2_MASK_CLR_OFFSET 0x944
158 #define ESR3_MASK_CLR_OFFSET 0x95c
159 #define ESR4_MASK_CLR_OFFSET 0x974
162 #define R5F_ESR0_SHIFT  0    /* esr0 = fifo underflow */
181 #define PERIOD_BYTES_MIN 0x100
192 	.period_bytes_max = 0x10000,
202 	.buffer_bytes_max = 4 * 0x8000,
212 	return snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(soc_runtime, 0), substream);  in cygnus_dai_get_dma_data()
260 	int status = 0;  in configure_ringbuf_regs()
269 		case 0:  in configure_ringbuf_regs()
270 			*p_rbuf = RINGBUF_REG_PLAYBACK(0);  in configure_ringbuf_regs()
288 		case 0:  in configure_ringbuf_regs()
289 			*p_rbuf = RINGBUF_REG_CAPTURE(0);  in configure_ringbuf_regs()
362 	dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "%s on port %d\n", __func__, aio->portnum);  in disable_intr()
382 	int ret = 0;  in cygnus_pcm_trigger()
431  *  0x1	I2S0_out port caused interrupt
432  *  0x2	I2S1_out port caused interrupt
433  *  0x4	I2S2_out port caused interrupt
434  *  0x8	SPDIF_out port caused interrupt
457 	for (port = 0; port < CYGNUS_MAX_PLAYBACK_PORTS; port++) {  in handle_playback_irq()
469 				"Underrun: esr0=0x%x, esr1=0x%x esr3=0x%x\n",  in handle_playback_irq()
495  *  0x1	I2S0_in port caused interrupt
496  *  0x2	I2S1_in port caused interrupt
497  *  0x4	I2S2_in port caused interrupt
518 	for (port = 0; port < CYGNUS_MAX_CAPTURE_PORTS; port++) {  in handle_capture_irq()
530 				"Overflow: esr2=0x%x\n", esr_status2);  in handle_capture_irq()
553 	 *  0		ESR0 (playback FIFO interrupt)  in cygnus_dma_irq()
593 	dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "%s port %d\n", __func__, aio->portnum);  in cygnus_pcm_open()
597 	ret = snd_pcm_hw_constraint_step(runtime, 0,  in cygnus_pcm_open()
599 	if (ret < 0)  in cygnus_pcm_open()
602 	ret = snd_pcm_hw_constraint_step(runtime, 0,  in cygnus_pcm_open()
604 	if (ret < 0)  in cygnus_pcm_open()
615 	return 0;  in cygnus_pcm_open()
626 	dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "%s  port %d\n", __func__, aio->portnum);  in cygnus_pcm_close()
634 		dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "freed  port %d\n", aio->portnum);  in cygnus_pcm_close()
636 	return 0;  in cygnus_pcm_close()
648 	dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "%s  port %d\n", __func__, aio->portnum);  in cygnus_pcm_hw_params()
653 	return 0;  in cygnus_pcm_hw_params()
663 	dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "%s  port %d\n", __func__, aio->portnum);  in cygnus_pcm_hw_free()
666 	return 0;  in cygnus_pcm_hw_free()
681 	dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "%s port %d\n", __func__, aio->portnum);  in cygnus_pcm_prepare()
686 	dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "%s (buf_size %lu) (period_size %lu)\n",  in cygnus_pcm_prepare()
695 	is_play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 1 : 0;  in cygnus_pcm_prepare()
700 	return 0;  in cygnus_pcm_prepare()
707 	unsigned int res = 0, cur = 0, base = 0;  in cygnus_pcm_pointer()
728 	res = (cur & 0x7fffffff) - (base & 0x7fffffff);  in cygnus_pcm_pointer()
748 	dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "%s: size 0x%zx @ %pK\n",  in cygnus_pcm_preallocate_dma_buffer()
752 		dev_err(asoc_rtd_to_cpu(rtd, 0)->dev, "%s: dma_alloc failed\n", __func__);  in cygnus_pcm_preallocate_dma_buffer()
757 	return 0;  in cygnus_pcm_preallocate_dma_buffer()
815 	return 0;  in cygnus_dma_new()
833 	int rc = 0;  in cygnus_soc_platform_register()
845 					     NULL, 0);  in cygnus_soc_platform_register()
851 	return 0;  in cygnus_soc_platform_register()
856 	return 0;  in cygnus_soc_platform_unregister()