251 static inline void iputbyte(struct intel8x0m *chip, u32 offset, u8 val)  in iputbyte()  function
413 	iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);  in snd_intel8x0m_setup_periods()
415 	iputbyte(chip, port + ICH_REG_OFF_CIV, 0);  in snd_intel8x0m_setup_periods()
425 	iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);  in snd_intel8x0m_setup_periods()
457 	iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);  in snd_intel8x0m_update()
481 	iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);  in snd_intel8x0m_update()
546 	iputbyte(chip, port + ICH_REG_OFF_CR, val);  in snd_intel8x0m_pcm_trigger()
551 		iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);  in snd_intel8x0m_pcm_trigger()
951 		iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);  in snd_intel8x0m_chip_init()
954 		iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);  in snd_intel8x0m_chip_init()
969 		iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);  in snd_intel8x0m_free()
972 		iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);  in snd_intel8x0m_free()