105 #define OPTi9XX_MC_REG(n)	n  macro
343 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(4), 0xf0, 0xfc);  in snd_opti9xx_configure()
345 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(6), 0x02, 0x02);  in snd_opti9xx_configure()
350 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(1), 0x80, 0x80);  in snd_opti9xx_configure()
352 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(2), 0x00, 0x20);  in snd_opti9xx_configure()
354 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(3), 0xf0, 0xff);  in snd_opti9xx_configure()
357 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(5), 0x02, 0x02);  in snd_opti9xx_configure()
360 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(5), 0x00, 0x02);  in snd_opti9xx_configure()
366 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(1), 0x80, 0x80);  in snd_opti9xx_configure()
367 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(2), 0x00, 0x20);  in snd_opti9xx_configure()
371 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(4), 0x00, 0x0c);  in snd_opti9xx_configure()
373 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(5), 0x02, 0x02);  in snd_opti9xx_configure()
375 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(5), 0x00, 0x02);  in snd_opti9xx_configure()
382 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(20), 0x04, 0x0c);  in snd_opti9xx_configure()
390 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(21), 0x82, 0xff);  in snd_opti9xx_configure()
395 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(26), 0x01, 0x01);  in snd_opti9xx_configure()
399 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(6), 0x02, 0x03);  in snd_opti9xx_configure()
400 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(3), 0x00, 0xff);  in snd_opti9xx_configure()
401 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(4), 0x10 |  in snd_opti9xx_configure()
404 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(5), 0x20, 0xbf);  in snd_opti9xx_configure()
435 	snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(1), wss_base_bits << 4, 0x30);  in snd_opti9xx_configure()
496 	snd_opti9xx_write(chip, OPTi9XX_MC_REG(3), (irq_bits << 3 | dma_bits));  in snd_opti9xx_configure()
542 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(6),  in snd_opti9xx_configure()
650 	status = snd_opti9xx_read(chip, OPTi9XX_MC_REG(11));  in snd_opti93x_interrupt()
675 	value = snd_opti9xx_read(chip, OPTi9XX_MC_REG(1));  in snd_opti9xx_read_check()
676 	if (value != 0xff && value != inb(chip->mc_base + OPTi9XX_MC_REG(1)))  in snd_opti9xx_read_check()
677 		if (value == snd_opti9xx_read(chip, OPTi9XX_MC_REG(1)))  in snd_opti9xx_read_check()
690 	value = snd_opti9xx_read(chip, OPTi9XX_MC_REG(7));  in snd_opti9xx_read_check()
691 	snd_opti9xx_write(chip, OPTi9XX_MC_REG(7), 0xff - value);  in snd_opti9xx_read_check()
692 	if (snd_opti9xx_read(chip, OPTi9XX_MC_REG(7)) == 0xff - value)  in snd_opti9xx_read_check()
910 			snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(2),
915 				snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(2),