uapi/drm/drm_fourcc.h

46  * format and data layout of the buffer, and should be the only way to describe
49  * Having multiple fourcc:modifier pairs which describe the same layout should
206  * then V), but the exact Linear layout is undefined.
349  * When adding a new token please document the layout with a code comment,
365  * In future cases where a generic layout is identified before merging with a
389  * Linear Layout
391  * Just plain linear layout. Note that this is different from no specifying any
401  * Intel X-tiling layout
403  * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
404  * in row-major layout. Within the tile bytes are laid out row-major, with
408  * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
411  * identify the layout in a simple way for i915-specific userspace, which
418  * Intel Y-tiling layout
420  * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
421  * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
426  * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
429  * identify the layout in a simple way for i915-specific userspace, which
436  * Intel Yf-tiling layout
438  * This is a tiled layout using 4Kb tiles in row-major layout.
440  * are arranged in four groups (two wide, two high) with column-major layout.
512  * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
513  * layout. For YCbCr formats Cb/Cr components are taken in such a way that
534  * Vivante 4x4 tiling layout
536  * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
537  * layout.
542  * Vivante 64x64 super-tiling layout
544  * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
546  * major layout.
554  * Vivante 4x4 tiling layout for dual-pipe
556  * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
558  * compared to the non-split tiled layout.
563  * Vivante 64x64 super-tiling layout for dual-pipe
565  * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
567  * therefore halved compared to the non-split super-tiled layout.
574  * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
581  * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80,
584  * Pixels are arranged in Groups of Bytes (GOBs).  GOB size and layout varies
601  *  4:4  -     Must be 1, to indicate block-linear layout.  Necessary for
618  *             tables of all GPUs >= NV50.  It affects the exact layout of bits
626  *             since the modifier should define the layout of the associated
632  *             kind and bit layout has changed at various points.
639  * 22:22 s     Sector layout.  On Tegra GPUs prior to Xavier, there is a further
641  *             page kind and block linear swizzles.  This causes the layout of
645  *               0 = Tegra K1 - Tegra Parker/TX2 Layout.
646  *               1 = Desktop GPU and Tegra Xavier+ Layout
651  *               1 = ROP/3D, layout 1, exact compression format implied by Page
653  *               2 = ROP/3D, layout 2, exact compression format implied by Page
671 /* To grandfather in prior block linear format modifiers to the above layout,
687  * 16Bx2 Block Linear layout, used by Tegra K1 and later
743  * This is the primary layout that the V3D GPU can texture from (it
891  * AFBC sparse layout
912  * AFBC tiled layout
914  * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
918  * When the tiled layout is used, the buffer size (in pixels) must be aligned
934  * Indicates that the buffer is allocated in a layout safe for front-buffer
951  * The buffer layout is the same as for AFBC buffers without USM set, this only
997  * The first 8 bits of the mode defines the layout, then the following 8 bits
998  * defines the options changing the layout.
1001  * combinations of layout and options.
1016  * Amlogic FBC Basic Layout
1018  * The basic layout is composed of:
1023  * This layout is transferrable between Amlogic SoCs supporting this modifier.
1028  * Amlogic FBC Scatter Memory layout
1031  * frames content to optimize memory access and layout.
1038  * Due to the nature of the layout, these buffers are not expected to
1047 /* Amlogic FBC Layout Options Bit Mask */
1056  * This mode reduces body layout to 3072 bytes per 64x32 superblock with
1057  * the basic layout and 3200 bytes per 64x32 superblock combined with
1058  * the scatter layout.