Lines Matching defs:hdac_bus

284 struct hdac_bus {  struct
286 	const struct hdac_bus_ops *ops;  argument
287 	const struct hdac_ext_bus_ops *ext_ops;
290 	unsigned long addr;
291 	void __iomem *remap_addr;
292 	int irq;
294 	void __iomem *ppcap;
295 	void __iomem *spbcap;
296 	void __iomem *mlcap;
297 	void __iomem *gtscap;
298 	void __iomem *drsmcap;
301 	struct list_head codec_list;
302 	unsigned int num_codecs;
305 	struct hdac_device *caddr_tbl[HDA_MAX_CODEC_ADDRESS + 1];
308 	u32 unsol_queue[HDA_UNSOL_QUEUE_SIZE * 2]; /* ring buffer */
309 	unsigned int unsol_rp, unsol_wp;
310 	struct work_struct unsol_work;
313 	unsigned long codec_mask;
316 	unsigned long codec_powered;
319 	struct hdac_rb corb;
320 	struct hdac_rb rirb;
321 	unsigned int last_cmd[HDA_MAX_CODECS];	/* last sent command */
322 	wait_queue_head_t rirb_wq;
325 	struct snd_dma_buffer rb;
326 	struct snd_dma_buffer posbuf;
327 	int dma_type;			/* SNDRV_DMA_TYPE_XXX for CORB/RIRB */
330 	struct list_head stream_list;
333 	bool chip_init:1;		/* h/w initialized */
336 	bool aligned_mmio:1;		/* aligned MMIO access */
337 	bool sync_write:1;		/* sync after verb write */
338 	bool use_posbuf:1;		/* use position buffer */
339 	bool snoop:1;			/* enable snooping */
340 	bool align_bdle_4k:1;		/* BDLE align 4K boundary */
341 	bool reverse_assign:1;		/* assign devices in reverse order */
342 	bool corbrp_self_clear:1;	/* CORBRP clears itself after reset */
343 	bool polling_mode:1;
344 	bool needs_damn_long_delay:1;
346 	int poll_count;
348 	int bdl_pos_adj;		/* BDL position adjustment */
351 	unsigned int dma_stop_delay;
375 int snd_hdac_bus_init(struct hdac_bus *bus, struct device *dev,  argument