Lines Matching +full:number +full:- +full:of +full:- +full:wires
1 /* SPDX-License-Identifier: GPL-2.0-or-later
26 * INTERFACES between SPI master-side drivers and SPI slave protocol handlers,
32 * struct spi_statistics - statistics for spi transfers
35 * @messages: number of spi-messages handled
36 * @transfers: number of spi_transfers handled
37 * @errors: number of errors during spi_transfer
38 * @timedout: number of timeouts during spi_transfer
40 * @spi_sync: number of times spi_sync is used
42 * number of times spi_sync is executed immediately
44 * @spi_async: number of times spi_async is used
46 * @bytes: number of bytes transferred to/from device
47 * @bytes_tx: number of bytes sent to device
48 * @bytes_rx: number of bytes received from device
54 * number of transfers that have been split because of
86 spin_lock_irqsave(&(stats)->lock, flags); \
87 (stats)->field += count; \
88 spin_unlock_irqrestore(&(stats)->lock, flags); \
95 * struct spi_delay - SPI delay information
111 * struct spi_device - Controller side proxy for an SPI slave device
112 * @dev: Driver model representation of the device.
114 * @master: Copy of controller, for backwards compatibility.
125 * like eight or 12 bits are common. In-memory wordsizes are
126 * powers of two bytes (e.g. 20 bit samples use 32 bits).
131 * @irq: Negative, or the number passed to request_irq() to receive
134 * @controller_data: Board-specific definitions for controller, such as
136 * @modalias: Name of the driver to use with this device, or an alias
139 * @driver_override: If the name of a driver is written to this attribute, then
141 * @cs_gpio: LEGACY: gpio number of the chipselect line (optional, -ENOENT when
144 * @cs_gpiod: gpio descriptor of the chipselect line (optional, NULL when
147 * words of a transfer
158 * information about how this particular board wires the chip's pins.
176 #define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */
181 #define SPI_TX_DUAL 0x100 /* transmit with 2 wires */
182 #define SPI_TX_QUAD 0x200 /* transmit with 4 wires */
183 #define SPI_RX_DUAL 0x400 /* receive with 2 wires */
184 #define SPI_RX_QUAD 0x800 /* receive with 4 wires */
186 #define SPI_TX_OCTAL 0x2000 /* transmit with 8 wires */
187 #define SPI_RX_OCTAL 0x4000 /* receive with 8 wires */
196 struct spi_delay word_delay; /* inter-word delay */
207 * - memory packing (12 bit samples into low bits, others zeroed)
208 * - priority
209 * - chipselect delays
210 * - ...
222 return (spi && get_device(&spi->dev)) ? spi : NULL; in spi_dev_get()
228 put_device(&spi->dev); in spi_dev_put()
234 return spi->controller_state; in spi_get_ctldata()
239 spi->controller_state = state; in spi_set_ctldata()
246 dev_set_drvdata(&spi->dev, data); in spi_set_drvdata()
251 return dev_get_drvdata(&spi->dev); in spi_get_drvdata()
258 * struct spi_driver - Host side "protocol" driver
259 * @id_table: List of SPI devices supported by this driver
268 * field of this structure.
270 * This represents the kind of device driver that uses SPI messages to
271 * interact with the hardware at the other end of a SPI link. It's called
279 * Examples of such upper levels include frameworks like MTD, networking,
300 * spi_unregister_driver - reverse effect of spi_register_driver
307 driver_unregister(&sdrv->driver); in spi_unregister_driver()
315 * module_spi_driver() - Helper macro for registering a SPI driver
319 * init/exit. This eliminates a lot of boilerplate. Each module may only
327 * struct spi_controller - interface to SPI master or slave controller
330 * @bus_num: board-specific (and often SOC-specific) identifier for a
339 * @bits_per_word_mask: A mask indicating which values of bits_per_word are
354 * @bus_lock_mutex: mutex for exclusion of multiple callers
363 * delay interms of clock counts
365 * @cleanup: frees controller-specific state
373 * @cur_msg: the currently in-flight message
375 * in-flight message
386 * @max_dma_len: Maximum length of a DMA transfer for the device.
399 * @set_cs: set the logic level of the chip select line. May be called
406 * - return 0 if the transfer is finished,
407 * - return 1 if the transfer is still in progress. When
415 * in the generic implementation of transfer_one_message().
426 * @cs_gpios: LEGACY: array of GPIO descs to use as chip select lines; one per
427 * CS number. Any individual value may be -ENOENT for CS lines that
430 * @cs_gpiods: Array of GPIO descs to use as chip select lines; one per CS
431 * number. Any individual value may be NULL for CS lines that
446 * @dummy_rx: dummy receive buffer for full-duplex devices
447 * @dummy_tx: dummy transmit buffer for full-duplex devices
452 * time snapshot in @spi_transfer->ptp_sts as close as possible to the
453 * moment in time when @spi_transfer->ptp_sts_word_pre and
454 * @spi_transfer->ptp_sts_word_post were transmitted.
456 * close to the driver hand-over as possible.
468 * a queue of spi_message transactions, copying data between CPU memory and
478 * board-specific. usually that simplifies to being SOC-specific.
480 * and one board's schematics might show it using SPI-2. software
486 * might use board-specific GPIOs.
501 /* bitmask of supported bits_per_word for transfers */
503 #define SPI_BPW_MASK(bits) BIT((bits) - 1)
504 #define SPI_BPW_RANGE_MASK(min, max) GENMASK((max) - 1, (min) - 1)
563 * + For now there's no remove-from-queue operation, or
632 * of transfer_one_message() provied by the core.
640 /* Optimized handlers for SPI memory-like operations. */
677 * transfers (needed e.g. for reading the time of POSIX clocks)
690 return dev_get_drvdata(&ctlr->dev); in spi_controller_get_devdata()
696 dev_set_drvdata(&ctlr->dev, data); in spi_controller_set_devdata()
701 if (!ctlr || !get_device(&ctlr->dev)) in spi_controller_get()
709 put_device(&ctlr->dev); in spi_controller_put()
714 return IS_ENABLED(CONFIG_SPI_SLAVE) && ctlr->slave; in spi_controller_is_slave()
788 * struct spi_res - spi resource management structure
791 * @data: extra data allocated for the specific use-case
793 * this is based on ideas from devres, but focused on life-cycle
811 /*---------------------------------------------------------------------------*/
816 * Protocol drivers use a queue of spi_messages, each transferring data
819 * The spi_messages themselves consist of a series of read+write transfer
820 * segments. Those segments always read the same number of bits as they
822 * pointer. (This is unlike most types of I/O API, because SPI hardware
825 * NOTE: Allocation of spi_transfer and spi_message memory is entirely
826 * up to the protocol driver, which guarantees the integrity of both (as
831 * struct spi_transfer - a read/write buffer pair
832 * @tx_buf: data to be written (dma-safe memory), or NULL
833 * @rx_buf: data to be read (dma-safe memory), or NULL
834 * @tx_dma: DMA address of tx_buf, if @spi_message.is_dma_mapped
835 * @rx_dma: DMA address of rx_buf, if @spi_message.is_dma_mapped
836 * @tx_nbits: number of bits used for writing. If 0 the default
838 * @rx_nbits: number of bits used for reading. If 0 the default
840 * @len: size of rx and tx buffers (in bytes)
856 * @effective_speed_hz: the effective SCK-speed that was used to
870 * If the core takes care of the timestamp (if @ptp_sts_supported is false
872 * @ptp_sts_word_post to the length of the transfer. This is done
873 * purposefully (instead of setting to spi_transfer->len - 1) to denote
874 * that a transfer-level snapshot taken from within the driver may still
875 * be of higher quality.
878 * hardware has some sort of assist for retrieving exact transfer timing,
888 * SPI transfers always write the same number of bytes as they read.
898 * shifting out three bytes with word size of sixteen or twenty bits;
901 * In-memory data values are always in native CPU byte order, translated
902 * from the wire byte order (big-endian except with SPI_LSB_FIRST). So
906 * When the word size of the SPI transfer is not a power-of-two multiple
907 * of eight bits, those in-memory words include extra bits. In-memory
908 * words are always seen by protocol drivers as right-justified, so the
916 * used to make the chipselect briefly go inactive in the middle of the
918 * a chip command, letting a single spi_message perform all of group of
922 * stay selected until the next transfer. On multi-device SPI busses
926 * Some devices need protocol transactions to be built from a series of
927 * spi_message submissions, where the content of one message is determined
928 * by the results of previous messages and where the whole transaction
932 * from device through @tx_nbits and @rx_nbits. In Bi-direction, these
938 * Zero-initialize every field you don't set up explicitly, to
946 * spi_message.is_dma_mapped reports a pre-existing mapping
988 * struct spi_message - one multi-segment SPI transaction
989 * @transfers: list of transfer segments in this transaction
995 * @frame_length: the total number of bytes in the message
996 * @actual_length: the total number of bytes that were transferred in all
1003 * A @spi_message is used to execute an atomic sequence of data transfers,
1013 * Zero-initialize every field you don't set up explicitly, to
1024 /* REVISIT: we might want a flag affecting the behavior of the
1029 * Some controller drivers (message-at-a-time queue processing)
1031 * others (with multi-message pipelines) could need a flag to
1049 /* list of spi_res reources when the spi message is processed */
1057 INIT_LIST_HEAD(&m->transfers); in spi_message_init_no_memset()
1058 INIT_LIST_HEAD(&m->resources); in spi_message_init_no_memset()
1070 list_add_tail(&t->transfer_list, &m->transfers); in spi_message_add_tail()
1076 list_del(&t->transfer_list); in spi_transfer_del()
1084 if (t->delay_usecs) { in spi_transfer_delay_exec()
1085 d.value = t->delay_usecs; in spi_transfer_delay_exec()
1090 return spi_delay_exec(&t->delay, t); in spi_transfer_delay_exec()
1094 * spi_message_init_with_transfers - Initialize spi_message and append transfers
1096 * @xfers: An array of spi transfers
1097 * @num_xfers: Number of items in the xfer array
1154 struct spi_controller *ctlr = spi->controller; in spi_max_message_size()
1156 if (!ctlr->max_message_size) in spi_max_message_size()
1158 return ctlr->max_message_size(spi); in spi_max_message_size()
1164 struct spi_controller *ctlr = spi->controller; in spi_max_transfer_size()
1168 if (ctlr->max_transfer_size) in spi_max_transfer_size()
1169 tr_max = ctlr->max_transfer_size(spi); in spi_max_transfer_size()
1176 * spi_is_bpw_supported - Check if bits per word is supported
1187 u32 bpw_mask = spi->master->bits_per_word_mask; in spi_is_bpw_supported()
1195 /*---------------------------------------------------------------------------*/
1197 /* SPI transfer replacement methods which make use of spi_res */
1204 * struct spi_replaced_transfers - structure describing the spi_transfer
1213 * are to get re-inserted
1214 * @inserted: number of transfers inserted
1215 * @inserted_transfers: array of spi_transfers of array-size @inserted,
1240 /*---------------------------------------------------------------------------*/
1249 /*---------------------------------------------------------------------------*/
1262 * spi_sync_transfer - synchronous SPI data transfer
1264 * @xfers: An array of spi_transfers
1265 * @num_xfers: Number of items in the xfer array
1268 * Does a synchronous SPI data transfer of the given spi_transfer array.
1286 * spi_write - SPI synchronous write
1309 * spi_read - SPI synchronous read
1337 * spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read
1344 * Return: the (unsigned) eight bit number returned by the
1359 * spi_w8r16 - SPI synchronous 8 bit write followed by 16 bit read
1364 * The number is returned in wire-order, which is at least sometimes
1365 * big-endian.
1369 * Return: the (unsigned) sixteen bit number returned by the
1384 * spi_w8r16be - SPI synchronous 8 bit write followed by 16 bit big-endian read
1390 * convert the read 16 bit data word from big-endian to native endianness.
1394 * Return: the (unsigned) sixteen bit number returned by the device in cpu
1410 /*---------------------------------------------------------------------------*/
1423 * parport adapters, or microcontrollers acting as USB-to-SPI bridges.
1427 * struct spi_board_info - board-specific template for a SPI device
1430 * data stored there is driver-specific.
1436 * from the chip datasheet and board-specific signal quality issues.
1443 * possibly presence of an inverter in the chipselect path.
1451 * be stored in tables of board-specific device descriptors, which are
1477 /* bus_num is board specific and matches the bus_num of some
1487 * where the default of SPI_CS_HIGH = 0 is wrong.
1496 * - quirks like clock rate mattering when not selected
1538 return list_is_last(&xfer->transfer_list, &ctlr->cur_msg->transfers); in spi_transfer_is_last()
1541 /* OF support code */