312 struct pci_dev {  struct
313 	struct list_head bus_list;	/* Node in per-bus list */
314 	struct pci_bus	*bus;		/* Bus this device is on */
315 	struct pci_bus	*subordinate;	/* Bus this device bridges to */
317 	void		*sysdata;	/* Hook for sys-specific extension */
318 	struct proc_dir_entry *procent;	/* Device entry in /proc/bus/pci */
319 	struct pci_slot	*slot;		/* Physical slot this device is in */
321 	unsigned int	devfn;		/* Encoded device & function index */
322 	unsigned short	vendor;
323 	unsigned short	device;
324 	unsigned short	subsystem_vendor;
325 	unsigned short	subsystem_device;
326 	unsigned int	class;		/* 3 bytes: (base,sub,prog-if) */
327 	u8		revision;	/* PCI revision, low byte of class word */
328 	u8		hdr_type;	/* PCI header type (`multi' flag masked out) */
330 	u16		aer_cap;	/* AER capability offset */
331 	struct aer_stats *aer_stats;	/* AER stats for this device */
333 	u8		pcie_cap;	/* PCIe capability offset */
334 	u8		msi_cap;	/* MSI capability offset */
335 	u8		msix_cap;	/* MSI-X capability offset */
336 	u8		pcie_mpss:3;	/* PCIe Max Payload Size Supported */
337 	u8		rom_base_reg;	/* Config register controlling ROM */
338 	u8		pin;		/* Interrupt pin this device uses */
339 	u16		pcie_flags_reg;	/* Cached PCIe Capabilities Register */
340 	unsigned long	*dma_alias_mask;/* Mask of enabled devfn aliases */
342 	struct pci_driver *driver;	/* Driver bound to this device */
343 	u64		dma_mask;	/* Mask of the bits of bus address this
349 	struct device_dma_parameters dma_parms;
351 	pci_power_t	current_state;	/* Current operating state. In ACPI,
354 	unsigned int	imm_ready:1;	/* Supports Immediate Readiness */
355 	u8		pm_cap;		/* PM capability offset */
356 	unsigned int	pme_support:5;	/* Bitmask of states from which PME#
358 	unsigned int	pme_poll:1;	/* Poll device's PME status bit */
359 	unsigned int	d1_support:1;	/* Low power state D1 is supported */
360 	unsigned int	d2_support:1;	/* Low power state D2 is supported */
361 	unsigned int	no_d1d2:1;	/* D1 and D2 are forbidden */
362 	unsigned int	no_d3cold:1;	/* D3cold is forbidden */
363 	unsigned int	bridge_d3:1;	/* Allow D3 for bridge */
364 	unsigned int	d3cold_allowed:1;	/* D3cold is allowed by user */
365 	unsigned int	mmio_always_on:1;	/* Disallow turning off io/mem
367 	unsigned int	wakeup_prepared:1;
368 	unsigned int	runtime_d3cold:1;	/* Whether go through runtime
372 	unsigned int	skip_bus_pm:1;	/* Internal: Skip bus-level PM */
373 	unsigned int	ignore_hotplug:1;	/* Ignore hotplug events */
374 	unsigned int	hotplug_user_indicators:1; /* SlotCtl indicators
377 	unsigned int	clear_retrain_link:1;	/* Need to clear Retrain Link
379 	unsigned int	d3hot_delay;	/* D3hot->D0 transition time in ms */
380 	unsigned int	d3cold_delay;	/* D3cold->D0 transition time in ms */
383 	struct pcie_link_state	*link_state;	/* ASPM link state */
384 	unsigned int	ltr_path:1;	/* Latency Tolerance Reporting
386 	int		l1ss;		/* L1SS Capability pointer */
388 	unsigned int	eetlp_prefix_path:1;	/* End-to-End TLP Prefix */
390 	pci_channel_state_t error_state;	/* Current connectivity state */
391 	struct device	dev;			/* Generic device interface */
393 	int		cfg_size;		/* Size of config space */
399 	unsigned int	irq;
400 	struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
402 	bool		match_driver;		/* Skip attaching driver */
404 	unsigned int	transparent:1;		/* Subtractive decode bridge */
405 	unsigned int	io_window:1;		/* Bridge has I/O window */
406 	unsigned int	pref_window:1;		/* Bridge has pref mem window */
407 	unsigned int	pref_64_window:1;	/* Pref mem window is 64-bit */
408 	unsigned int	multifunction:1;	/* Multi-function device */
410 	unsigned int	is_busmaster:1;		/* Is busmaster */
411 	unsigned int	no_msi:1;		/* May not use MSI */
412 	unsigned int	no_64bit_msi:1;		/* May only use 32-bit MSIs */
413 	unsigned int	block_cfg_access:1;	/* Config space access blocked */
414 	unsigned int	broken_parity_status:1;	/* Generates false positive parity */
415 	unsigned int	irq_reroute_variant:2;	/* Needs IRQ rerouting variant */
416 	unsigned int	msi_enabled:1;
417 	unsigned int	msix_enabled:1;
418 	unsigned int	ari_enabled:1;		/* ARI forwarding */
419 	unsigned int	ats_enabled:1;		/* Address Translation Svc */
420 	unsigned int	pasid_enabled:1;	/* Process Address Space ID */
421 	unsigned int	pri_enabled:1;		/* Page Request Interface */
422 	unsigned int	is_managed:1;
423 	unsigned int	needs_freset:1;		/* Requires fundamental reset */
424 	unsigned int	state_saved:1;
425 	unsigned int	is_physfn:1;
426 	unsigned int	is_virtfn:1;
427 	unsigned int	reset_fn:1;
428 	unsigned int	is_hotplug_bridge:1;
429 	unsigned int	shpc_managed:1;		/* SHPC owned by shpchp */
453 	pci_dev_flags_t dev_flags;  argument
454 	atomic_t	enable_cnt;	/* pci_enable_device has been called */
457 	atomic_t	sysfs_init_cnt;		/* pci_create_sysfs_dev_files has been called */
459 	u32		saved_config_space[16]; /* Config space saved at suspend time */
460 	struct hlist_head saved_cap_space;
461 	struct bin_attribute *rom_attr;		/* Attribute descriptor for sysfs ROM entry */
462 	int		rom_attr_enabled;	/* Display of ROM attribute enabled? */
486 		struct pci_dev		*physfn;	/* VF: related PF */  argument
488 	u16		ats_cap;	/* ATS Capability offset */
489 	u8		ats_stu;	/* ATS Smallest Translation Unit */
492 	u16		pri_cap;	/* PRI Capability offset */
516 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)  in pci_physfn()  argument
708 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)  in pci_dev_msi_enabled()
713 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }  in pci_dev_msi_enabled()