linux/mfd/tmio.h

1 /* SPDX-License-Identifier: GPL-2.0 */
28 #define sd_config_write8(base, shift, reg, val) \  argument
29 	tmio_iowrite8((val), (base) + ((reg) << (shift)))
30 #define sd_config_write16(base, shift, reg, val) \  argument
31 	tmio_iowrite16((val), (base) + ((reg) << (shift)))
32 #define sd_config_write32(base, shift, reg, val) \  argument
34 		tmio_iowrite16((val), (base) + ((reg) << (shift)));   \
35 		tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \
40  * Some controllers can support a 2-byte block size when the bus width
41  * is configured in 4-bit mode.
43 #define TMIO_MMC_BLKSZ_2BYTES		BIT(1)
47 #define TMIO_MMC_SDIO_IRQ		BIT(2)
49 /* Some features are only available or tested on R-Car Gen2 or later */
50 #define TMIO_MMC_MIN_RCAR2		BIT(3)
56 #define TMIO_MMC_HAS_IDLE_WAIT		BIT(4)
58 /* BIT(5) is unused */
62  * issue/non-issue register
64 #define TMIO_MMC_HAVE_CMD12_CTRL	BIT(7)
67 #define TMIO_MMC_SDIO_STATUS_SETBITS	BIT(8)
70  * Some controllers have a 32-bit wide data port register
72 #define TMIO_MMC_32BIT_DATA_PORT	BIT(9)
77 #define TMIO_MMC_CLK_ACTUAL		BIT(10)
79 /* Some controllers have a CBSY bit */
80 #define TMIO_MMC_HAVE_CBSY		BIT(11)
82 int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
83 int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
84 void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state);
85 void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state);