Lines Matching +full:6 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Author: Chris Zhong <zyw@rock-chips.com>
8 * Author: Zhang Qing <zhangqing@rock-chips.com>
283 #define RK816_IRQ_RTC_ALARM 6
294 #define RK816_IRQ_PWRON_FALL_MSK BIT(5)
295 #define RK816_IRQ_PWRON_RISE_MSK BIT(6)
296 #define RK816_IRQ_VB_LOW_MSK BIT(1)
297 #define RK816_IRQ_PWRON_MSK BIT(2)
298 #define RK816_IRQ_PWRON_LP_MSK BIT(3)
299 #define RK816_IRQ_HOTDIE_MSK BIT(4)
300 #define RK816_IRQ_RTC_ALARM_MSK BIT(5)
301 #define RK816_IRQ_RTC_PERIOD_MSK BIT(6)
302 #define RK816_IRQ_USB_OV_MSK BIT(7)
303 #define RK816_IRQ_PLUG_IN_MSK BIT(0)
304 #define RK816_IRQ_PLUG_OUT_MSK BIT(1)
305 #define RK816_IRQ_CHG_OK_MSK BIT(2)
306 #define RK816_IRQ_CHG_TE_MSK BIT(3)
307 #define RK816_IRQ_CHG_TS_MSK BIT(4)
308 #define RK816_IRQ_CHG_CVTLIM_MSK BIT(6)
309 #define RK816_IRQ_DISCHG_ILIM_MSK BIT(7)
320 #define RK816_PWR_RISE_INT_STATUS (0x1 << 6)
337 #define BUCK1_2_IMAX_MAX (0x3 << 6)
503 #define RK818_H5V_EN BIT(0)
504 #define RK818_REF_RDY_CTRL BIT(1)
571 #define RK805_IRQ_RTC_PERIOD 6
574 * When PMIC irq occurs, regmap-irq.c will traverse all PMIC child
583 #define RK805_IRQ_PWRON_RISE_MSK BIT(0)
584 #define RK805_IRQ_VB_LOW_MSK BIT(1)
585 #define RK805_IRQ_PWRON_MSK BIT(2)
586 #define RK805_IRQ_PWRON_LP_MSK BIT(3)
587 #define RK805_IRQ_HOTDIE_MSK BIT(4)
588 #define RK805_IRQ_RTC_ALARM_MSK BIT(5)
589 #define RK805_IRQ_RTC_PERIOD_MSK BIT(6)
590 #define RK805_IRQ_PWRON_FALL_MSK BIT(7)
592 #define RK805_PWR_RISE_INT_STATUS BIT(0)
593 #define RK805_VB_LOW_INT_STATUS BIT(1)
594 #define RK805_PWRON_INT_STATUS BIT(2)
595 #define RK805_PWRON_LP_INT_STATUS BIT(3)
596 #define RK805_HOTDIE_INT_STATUS BIT(4)
597 #define RK805_ALARM_INT_STATUS BIT(5)
598 #define RK805_PERIOD_INT_STATUS BIT(6)
599 #define RK805_PWR_FALL_INT_STATUS BIT(7)
601 #define RK805_BUCK1_2_ILMAX_MASK (3 << 6)
603 #define RK805_RTC_PERIOD_INT_MASK (1 << 6)
608 #define RK805_SLP_LDO_EN_OFFSET -1
625 #define RK808_IRQ_RTC_PERIOD 6
630 #define RK808_IRQ_VOUT_LO_MSK BIT(0)
631 #define RK808_IRQ_VB_LO_MSK BIT(1)
632 #define RK808_IRQ_PWRON_MSK BIT(2)
633 #define RK808_IRQ_PWRON_LP_MSK BIT(3)
634 #define RK808_IRQ_HOTDIE_MSK BIT(4)
635 #define RK808_IRQ_RTC_ALARM_MSK BIT(5)
636 #define RK808_IRQ_RTC_PERIOD_MSK BIT(6)
637 #define RK808_IRQ_PLUG_IN_INT_MSK BIT(0)
638 #define RK808_IRQ_PLUG_OUT_INT_MSK BIT(1)
647 #define RK818_IRQ_RTC_PERIOD 6
658 #define RK818_IRQ_VOUT_LO_MSK BIT(0)
659 #define RK818_IRQ_VB_LO_MSK BIT(1)
660 #define RK818_IRQ_PWRON_MSK BIT(2)
661 #define RK818_IRQ_PWRON_LP_MSK BIT(3)
662 #define RK818_IRQ_HOTDIE_MSK BIT(4)
663 #define RK818_IRQ_RTC_ALARM_MSK BIT(5)
664 #define RK818_IRQ_RTC_PERIOD_MSK BIT(6)
665 #define RK818_IRQ_USB_OV_MSK BIT(7)
666 #define RK818_IRQ_PLUG_IN_MSK BIT(0)
667 #define RK818_IRQ_PLUG_OUT_MSK BIT(1)
668 #define RK818_IRQ_CHG_OK_MSK BIT(2)
669 #define RK818_IRQ_CHG_TE_MSK BIT(3)
670 #define RK818_IRQ_CHG_TS1_MSK BIT(4)
671 #define RK818_IRQ_TS2_MSK BIT(5)
672 #define RK818_IRQ_CHG_CVTLIM_MSK BIT(6)
673 #define RK818_IRQ_DISCHG_ILIM_MSK BIT(7)
678 #define BUCK1_EN_MASK BIT(0)
679 #define BUCK2_EN_MASK BIT(1)
680 #define BUCK3_EN_MASK BIT(2)
681 #define BUCK4_EN_MASK BIT(3)
682 #define BOOST_EN_MASK BIT(4)
683 #define LDO9_EN_MASK BIT(5)
684 #define SWITCH_EN_MASK BIT(6)
685 #define OTG_EN_MASK BIT(7)
687 #define BUCK1_EN_ENABLE BIT(0)
688 #define BUCK2_EN_ENABLE BIT(1)
689 #define BUCK3_EN_ENABLE BIT(2)
690 #define BUCK4_EN_ENABLE BIT(3)
691 #define BOOST_EN_ENABLE BIT(4)
692 #define LDO9_EN_ENABLE BIT(5)
693 #define SWITCH_EN_ENABLE BIT(6)
694 #define OTG_EN_ENABLE BIT(7)
696 #define BUCK1_SLP_SET_MASK BIT(0)
697 #define BUCK2_SLP_SET_MASK BIT(1)
698 #define BUCK3_SLP_SET_MASK BIT(2)
699 #define BUCK4_SLP_SET_MASK BIT(3)
700 #define BOOST_SLP_SET_MASK BIT(4)
701 #define LDO9_SLP_SET_MASK BIT(5)
702 #define SWITCH_SLP_SET_MASK BIT(6)
703 #define OTG_SLP_SET_MASK BIT(7)
705 #define BUCK1_SLP_SET_OFF BIT(0)
706 #define BUCK2_SLP_SET_OFF BIT(1)
707 #define BUCK3_SLP_SET_OFF BIT(2)
708 #define BUCK4_SLP_SET_OFF BIT(3)
709 #define BOOST_SLP_SET_OFF BIT(4)
710 #define LDO9_SLP_SET_OFF BIT(5)
711 #define SWITCH_SLP_SET_OFF BIT(6)
712 #define OTG_SLP_SET_OFF BIT(7)
715 #define BUCK1_SLP_SET_ON BIT(0)
716 #define BUCK2_SLP_SET_ON BIT(1)
717 #define BUCK3_SLP_SET_ON BIT(2)
718 #define BUCK4_SLP_SET_ON BIT(3)
719 #define BOOST_SLP_SET_ON BIT(4)
720 #define LDO9_SLP_SET_ON BIT(5)
721 #define SWITCH_SLP_SET_ON BIT(6)
722 #define OTG_SLP_SET_ON BIT(7)
724 #define VOUT_LO_MASK BIT(0)
725 #define VB_LO_MASK BIT(1)
726 #define PWRON_MASK BIT(2)
727 #define PWRON_LP_MASK BIT(3)
728 #define HOTDIE_MASK BIT(4)
729 #define RTC_ALARM_MASK BIT(5)
730 #define RTC_PERIOD_MASK BIT(6)
731 #define USB_OV_MASK BIT(7)
733 #define VOUT_LO_DISABLE BIT(0)
734 #define VB_LO_DISABLE BIT(1)
735 #define PWRON_DISABLE BIT(2)
736 #define PWRON_LP_DISABLE BIT(3)
737 #define HOTDIE_DISABLE BIT(4)
738 #define RTC_ALARM_DISABLE BIT(5)
739 #define RTC_PERIOD_DISABLE BIT(6)
740 #define USB_OV_INT_DISABLE BIT(7)
748 #define RTC_PERIOD_ENABLE (0 << 6)
751 #define PLUG_IN_MASK BIT(0)
752 #define PLUG_OUT_MASK BIT(1)
753 #define CHGOK_MASK BIT(2)
754 #define CHGTE_MASK BIT(3)
755 #define CHGTS1_MASK BIT(4)
756 #define TS2_MASK BIT(5)
757 #define CHG_CVTLIM_MASK BIT(6)
758 #define DISCHG_ILIM_MASK BIT(7)
760 #define PLUG_IN_DISABLE BIT(0)
761 #define PLUG_OUT_DISABLE BIT(1)
762 #define CHGOK_DISABLE BIT(2)
763 #define CHGTE_DISABLE BIT(3)
764 #define CHGTS1_DISABLE BIT(4)
765 #define TS2_DISABLE BIT(5)
766 #define CHG_CVTLIM_DISABLE BIT(6)
767 #define DISCHG_ILIM_DISABLE BIT(7)
769 #define PLUG_IN_ENABLE BIT(0)
770 #define PLUG_OUT_ENABLE BIT(1)
771 #define CHGOK_ENABLE BIT(2)
772 #define CHGTE_ENABLE BIT(3)
773 #define CHGTS1_ENABLE BIT(4)
774 #define TS2_ENABLE BIT(5)
775 #define CHG_CVTLIM_ENABLE BIT(6)
776 #define DISCHG_ILIM_ENABLE BIT(7)
800 #define SWITCH2_EN BIT(6)
801 #define SWITCH1_EN BIT(5)
802 #define DEV_OFF_RST BIT(3)
803 #define DEV_OFF BIT(0)
804 #define RTC_STOP BIT(0)
806 #define VB_LO_ACT BIT(4)
809 #define VOUT_LO_INT BIT(0)
810 #define CLK32KOUT2_EN BIT(0)
812 #define CLK32KOUT2_FUNC_MASK BIT(1)
821 #define PWM_MODE_MSK BIT(7)
822 #define FPWM_MODE BIT(7)
928 #define RK817_IRQ_RTC_PERIOD 6
952 #define RK817_RTC_CTRL_RSV4 BIT(4)
955 #define RK817_BUCK3_FB_RES_MSK BIT(6)
956 #define RK817_BUCK3_FB_RES_INTER BIT(6)
960 #define RK817_RAMP_RATE_OFFSET 6
974 #define RK817_TSD_TEMP_MSK BIT(6)
976 #define RK817_TSD_160 BIT(6)
978 #define RK817_CLK32KOUT2_EN BIT(7)
987 #define RK817_RST_FUNC_MSK (0x3 << 6)
988 #define RK817_RST_FUNC_SFT (6)
991 #define RK817_RST_FUNC_REG (0x1 << 6) /* reset the reg only */
993 #define RK817_SLPPOL_MSK BIT(5)
994 #define RK817_SLPPOL_H BIT(5)
998 #define RK817_INT_POL_MSK BIT(1)
999 #define RK817_INT_POL_H BIT(1)