Lines Matching refs:HIWORD_MASK

17 #define HIWORD_MASK(h, l)	((GENMASK((h), (l)) << 16) | GENMASK((h), (l)))  macro
22 #define GPIO0A0_SEL_MASK HIWORD_MASK(1, 0)
24 #define GPIO0A1_SEL_MASK HIWORD_MASK(3, 2)
26 #define GPIO0A2_SEL_MASK HIWORD_MASK(5, 4)
28 #define GPIO0A3_SEL_MASK HIWORD_MASK(7, 6)
30 #define GPIO0A4_SEL_MASK HIWORD_MASK(9, 8)
32 #define GPIO0A5_SEL_MASK HIWORD_MASK(11, 10)
34 #define GPIO0A6_SEL_MASK HIWORD_MASK(13, 12)
36 #define GPIO0A7_SEL_MASK HIWORD_MASK(15, 14)
39 #define GPIO0B0_SEL_MASK HIWORD_MASK(1, 0)
54 #define SW_TVE_DCLK_POL_MASK HIWORD_MASK(4, 4)
56 #define SW_TVE_DCLK_EN_MASK HIWORD_MASK(3, 3)
58 #define SW_DCLK_UPSAMPLE_EN_MASK HIWORD_MASK(2, 2)
60 #define SW_TVE_MODE_MASK HIWORD_MASK(1, 1)
62 #define SW_TVE_EN_MASK HIWORD_MASK(0, 0)
67 #define VDAC_ENVBG_MASK HIWORD_MASK(12, 12)
69 #define VDAC_ENSC0_MASK HIWORD_MASK(11, 11)
71 #define VDAC_ENEXTREF_MASK HIWORD_MASK(10, 10)
73 #define VDAC_ENDAC0_MASK HIWORD_MASK(9, 9)
75 #define VDAC_ENCTR2_MASK HIWORD_MASK(8, 8)
77 #define VDAC_ENCTR1_MASK HIWORD_MASK(7, 7)
79 #define VDAC_ENCTR0_MASK HIWORD_MASK(6, 6)
92 #define POSTDIV1_MASK HIWORD_MASK(14, 12)
94 #define FBDIV_MASK HIWORD_MASK(14, 12)
97 #define PLLPD0_MASK HIWORD_MASK(13, 13)
100 #define POSTDIV2_MASK HIWORD_MASK(8, 6)
102 #define REFDIV_MASK HIWORD_MASK(5, 0)
106 #define CLK_SPLL_MODE_MASK HIWORD_MASK(2, 0)
110 #define DCLK_CVBS_4X_DIV_CON_MASK HIWORD_MASK(12, 8)
116 #define DRESETN_CVBS_1X_MASK HIWORD_MASK(10, 10)
118 #define DRESETN_CVBS_4X_MASK HIWORD_MASK(9, 9)
120 #define PRESETN_CVBS_MASK HIWORD_MASK(8, 8)
122 #define PRESETN_GRF_MASK HIWORD_MASK(3, 3)