Lines Matching +full:7 +full:- +full:bit

1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Defining registers address and its bit definitions of MAX96745
29 #define PU_LF3 BIT(3)
30 #define PU_LF2 BIT(2)
31 #define PU_LF1 BIT(1)
32 #define PU_LF0 BIT(0)
35 #define RESET_ALL BIT(7)
36 #define SLEEP BIT(3)
39 #define CXTP_B BIT(2)
40 #define CXTP_A BIT(0)
43 #define LOCKED BIT(3)
44 #define ERROR BIT(2)
55 #define LINK_EN BIT(7)
59 #define RESET_LINK BIT(0)
60 #define RESET_ONESHOT BIT(1)
63 #define LINK_LOCKED BIT(0)
66 #define DIS_REM_CC BIT(7)
70 #define VID_TX_EN BIT(0)
76 #define PCLKDET_A BIT(7)
77 #define DRIFT_ERR_A BIT(6)
78 #define OVERFLOW_A BIT(5)
79 #define FIFO_WARN_A BIT(4)
80 #define LIM_HEART BIT(2)
83 #define VID_TX_ACTIVE_B BIT(7)
84 #define VID_TX_ACTIVE_A BIT(6)
87 #define PCLKDET_B BIT(7)
88 #define DRIFT_ERR_B BIT(6)
89 #define OVERFLOW_B BIT(5)
90 #define FIFO_WARN_B BIT(4)
93 #define RES_CFG BIT(7)
94 #define TX_COM_EN BIT(5)
95 #define GPIO_OUT BIT(4)
96 #define GPIO_IN BIT(3)
97 #define GPIO_OUT_DIS BIT(0)
100 #define PULL_UPDN_SEL GENMASK(7, 6)
101 #define OUT_TYPEC BIT(5)
105 #define OVR_RES_CFG BIT(7)
110 #define GPIO_IO_RX_EN BIT(5)
111 #define GPIO_OUT_LGC BIT(4)
112 #define GPIO_RX_EN_B BIT(3)
113 #define GPIO_TX_EN_B BIT(2)
114 #define GPIO_RX_EN_A BIT(1)
115 #define GPIO_TX_EN_A BIT(0)
118 #define FRCZEROPAD GENMASK(7, 6)
119 #define FRCZPEN BIT(5)
120 #define FRCSDGAIN BIT(4)
121 #define FRCSDEN BIT(3)
123 #define FRCEN BIT(0)
126 #define FRCDATAWIDTH BIT(3)
127 #define FRCASYNCEN BIT(2)
128 #define FRCHSPOL BIT(1)
129 #define FRCVSPOL BIT(0)
135 #define DPRX_TRAIN_STATE GENMASK(7, 4)
138 #define LINK_ENABLE BIT(0)
141 #define MAX_LANE_COUNT GENMASK(7, 0)
144 #define MAX_LINK_RATE GENMASK(7, 0)