include/linux/intel-iommu.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * Copyright © 2006-2015, Intel Corporation.
20 #include <linux/io-64-nonatomic-lo-hi.h>
28  * VT-d hardware uses 4KiB page size regardless of host page size.
32 #define VTD_PAGE_MASK		(((u64)-1) << VTD_PAGE_SHIFT)
33 #define VTD_PAGE_ALIGN(addr)	(((addr) + VTD_PAGE_SIZE - 1) & VTD_PAGE_MASK)
36 #define VTD_STRIDE_MASK         (((u64)-1) << VTD_STRIDE_SHIFT)
76 #define	DMAR_PHMBASE_REG 0x70	/* pmrr high base addr */
77 #define	DMAR_PHMLIMIT_REG 0x78	/* pmrr high limit */
282 #define DMA_FSTS_ITE (1 << 6) /* Invalidation Time-out Error */
294 #define dma_frcd_page_addr(d) (d & (((u64)-1) << PAGE_SHIFT))
306 		sts = op(iommu->reg + offset);				\
309 		if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\
347 #define QI_IOTLB_GRAN(gran) 	(((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4))
355 #define QI_CC_GRAN(gran)	(((u64)gran) >> (DMA_CCMD_INVL_GRANU_OFFSET-4))
381 /* QI Dev-IOTLB inv granu */
413 #define qi_shift(iommu)		(DMAR_IQ_SHIFT + !!ecap_smts((iommu)->ecap))
434 /* 1MB - maximum possible interrupt remapping table size */
476 #define sm_supported(iommu)	(intel_iommu_sm && ecap_smts((iommu)->ecap))
478 				 ecap_pasid((iommu)->ecap))
486  * 1-11: Reserved
487  * 12-63: Context Ptr (12 - (haw-1))
488  * 64-127: Reserved
499  * 2-3: translation type
500  * 12-63: address space root
501  * high 64 bits:
502  * 0-2: address width
503  * 3-6: aval
504  * 8-23: domain id
515  * When VT-d works in the scalable mode, it allows DMA translation to
538 					 * to VT-d spec, section 9.3 */
549 	/* adjusted guest address width, 0 is level 2 30-bit */
563 					 * The default pasid used for non-SVM
616 /* PCI domain-device relationship */
636 	struct device *dev; /* it's NULL for PCIe-to-PCI bridge */
645 	if (!ecap_coherent(iommu->ecap))  in __iommu_flush_cache()
658  * 2-6: reserved
660  * 8-10: available
662  * 12-63: Host physcial address
670 	pte->val = 0;  in dma_clear_pte()
676 	return pte->val & VTD_PAGE_MASK & (~DMA_FL_PTE_XD);  in dma_pte_addr()
678 	/* Must have a full atomic 64-bit read */  in dma_pte_addr()
679 	return  __cmpxchg64(&pte->val, 0ULL, 0ULL) &  in dma_pte_addr()
686 	return (pte->val & 3) != 0;  in dma_pte_present()
691 	return (pte->val & DMA_PTE_LARGE_PAGE);  in dma_pte_superpage()
727  * QI_OPT_WAIT_DRAIN - Wait for PRQ drain completion, spec 6.5.2.8.