Lines Matching defs:intel_iommu
571 struct intel_iommu { struct
572 void __iomem *reg; /* Pointer to hardware regs, virtual addr */
573 u64 reg_phys; /* physical address of hw register set */
574 u64 reg_size; /* size of hw register set */
575 u64 cap;
576 u64 ecap;
577 u64 vccap;
578 u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
579 raw_spinlock_t register_lock; /* protect register handling */
580 int seq_id; /* sequence id of the iommu */
581 int agaw; /* agaw of this iommu */
582 int msagaw; /* max sagaw of this iommu */
583 unsigned int irq, pr_irq;
584 u16 segment; /* PCI segment# */
585 unsigned char name[13]; /* Device Name */
588 unsigned long *domain_ids; /* bitmap of domains */
589 struct dmar_domain ***domains; /* ptr to domains */
590 spinlock_t lock; /* protect context, domain ids */
591 struct root_entry *root_entry; /* virtual address */
593 struct iommu_flush flush;
596 struct page_req_dsc *prq;
597 unsigned char prq_name[16]; /* Name for PRQ interrupt */
598 struct completion prq_complete;
599 struct ioasid_allocator_ops pasid_allocator; /* Custom allocator for PASIDs */
601 struct q_inval *qi; /* Queued invalidation info */
602 u32 *iommu_state; /* Store iommu states between suspend and resume.*/
605 struct ir_table *ir_table; /* Interrupt remapping info */
606 struct irq_domain *ir_domain;
607 struct irq_domain *ir_msi_domain;
609 struct iommu_device iommu; /* IOMMU core code handle */
610 int node;
611 u32 flags; /* Software defined flags */
613 struct dmar_drhd_unit *drhd;