Lines Matching defs:flags

307 	unsigned long		flags;  member
356 unsigned long flags; member
380 #define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \ argument
392 #define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags, \ argument
405 #define clk_hw_register_fixed_rate_parent_data(dev, name, parent_hw, flags, \ argument
421 flags, fixed_rate, \ argument
437 parent_hw, flags, fixed_rate, fixed_accuracy) \ argument
452 parent_data, flags, fixed_rate, fixed_accuracy) \ argument
489 u8 flags; member
522 #define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx, \ argument
539 #define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg, \ argument
556 #define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg, \ argument
615 u8 flags; member
673 #define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \ argument
690 #define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \ argument
708 #define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg, \ argument
727 #define clk_hw_register_divider_parent_data(dev, name, parent_data, flags, \ argument
747 #define clk_hw_register_divider_table(dev, name, parent_name, flags, reg, \ argument
767 #define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags, \ argument
789 flags, reg, shift, width, \ argument
835 u8 flags; member
863 #define clk_register_mux(dev, name, parent_names, num_parents, flags, reg, \ argument
869 flags, reg, shift, mask, clk_mux_flags, \ argument
875 #define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \ argument
881 #define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags, \ argument
887 flags, reg, shift, width, \ argument
965 u8 flags; member
1018 u8 flags; member
1149 u8 width, unsigned long flags) in divider_round_rate()
1158 u8 width, unsigned long flags, in divider_ro_round_rate()
1400 unsigned long *flags) in of_clk_detect_critical()