1189 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
1190 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
1391 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_max_link_rate()
1393 	return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);  in drm_dp_max_link_rate()
1397 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_max_lane_count()
1399 	return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;  in drm_dp_max_lane_count()
1403 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_enhanced_frame_cap()
1405 	return dpcd[DP_DPCD_REV] >= 0x11 &&  in drm_dp_enhanced_frame_cap()
1406 		(dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);  in drm_dp_enhanced_frame_cap()
1410 drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_fast_training_cap()
1412 	return dpcd[DP_DPCD_REV] >= 0x11 &&  in drm_dp_fast_training_cap()
1413 		(dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);  in drm_dp_fast_training_cap()
1417 drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_tps3_supported()
1419 	return dpcd[DP_DPCD_REV] >= 0x12 &&  in drm_dp_tps3_supported()
1420 		dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED;  in drm_dp_tps3_supported()
1424 drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_tps4_supported()
1426 	return dpcd[DP_DPCD_REV] >= 0x14 &&  in drm_dp_tps4_supported()
1427 		dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED;  in drm_dp_tps4_supported()
1431 drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_training_pattern_mask()
1433 	return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 :  in drm_dp_training_pattern_mask()
1438 drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_is_branch()
1440 	return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT;  in drm_dp_is_branch()
1482 drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_channel_coding_supported()
1484 	return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B;  in drm_dp_channel_coding_supported()
1488 drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_alternate_scrambler_reset_cap()
1490 	return dpcd[DP_EDP_CONFIGURATION_CAP] &  in drm_dp_alternate_scrambler_reset_cap()
1496 drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_sink_can_do_video_without_timing_msa()
1498 	return dpcd[DP_DOWN_STREAM_PORT_COUNT] &  in drm_dp_sink_can_do_video_without_timing_msa()
1644 			  u8 dpcd[DP_RECEIVER_CAP_SIZE]);
1653 				const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1655 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1657 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1660 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1662 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1665 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1668 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1671 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1673 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1676 						const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1680 			     const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1685 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1689 				      const u8 *dpcd,
1694 				const u8 dpcd[DP_RECEIVER_CAP_SIZE],