Lines Matching +full:610 +full:us
509 * offset 10 610 - Mailbox0
707 #define TSI148_LCSR_VMCTRL_ATO_32 (0<<16) /* 32 us */
708 #define TSI148_LCSR_VMCTRL_ATO_128 (1<<16) /* 128 us */
709 #define TSI148_LCSR_VMCTRL_ATO_512 (2<<16) /* 512 us */
717 #define TSI148_LCSR_VMCTRL_VTOFF_0 (0<<12) /* 0us */
718 #define TSI148_LCSR_VMCTRL_VTOFF_1 (1<<12) /* 1us */
719 #define TSI148_LCSR_VMCTRL_VTOFF_2 (2<<12) /* 2us */
720 #define TSI148_LCSR_VMCTRL_VTOFF_4 (3<<12) /* 4us */
721 #define TSI148_LCSR_VMCTRL_VTOFF_8 (4<<12) /* 8us */
722 #define TSI148_LCSR_VMCTRL_VTOFF_16 (5<<12) /* 16us */
723 #define TSI148_LCSR_VMCTRL_VTOFF_32 (6<<12) /* 32us */
724 #define TSI148_LCSR_VMCTRL_VTOFF_64 (7<<12) /* 64us */
727 #define TSI148_LCSR_VMCTRL_VTON_4 (0<<8) /* 8us */
728 #define TSI148_LCSR_VMCTRL_VTON_8 (1<<8) /* 8us */
729 #define TSI148_LCSR_VMCTRL_VTON_16 (2<<8) /* 16us */
730 #define TSI148_LCSR_VMCTRL_VTON_32 (3<<8) /* 32us */
731 #define TSI148_LCSR_VMCTRL_VTON_64 (4<<8) /* 64us */
732 #define TSI148_LCSR_VMCTRL_VTON_128 (5<<8) /* 128us */
733 #define TSI148_LCSR_VMCTRL_VTON_256 (6<<8) /* 256us */
734 #define TSI148_LCSR_VMCTRL_VTON_512 (7<<8) /* 512us */
781 #define TSI148_LCSR_VCTRL_GTO_8 (0<<0) /* 8 us */
782 #define TSI148_LCSR_VCTRL_GTO_16 (1<<0) /* 16 us */
783 #define TSI148_LCSR_VCTRL_GTO_32 (2<<0) /* 32 us */
784 #define TSI148_LCSR_VCTRL_GTO_64 (3<<0) /* 64 us */
785 #define TSI148_LCSR_VCTRL_GTO_128 (4<<0) /* 128 us */
786 #define TSI148_LCSR_VCTRL_GTO_256 (5<<0) /* 256 us */
787 #define TSI148_LCSR_VCTRL_GTO_512 (6<<0) /* 512 us */
992 #define TSI148_LCSR_VICR_IRQIF_1U (4<<18) /* 1us Clock */
998 #define TSI148_LCSR_VICR_IRQ2F_1U (4<<16) /* 1us Clock */
1219 #define TSI148_LCSR_DCTL_VBOT_0 (0<<8) /* VMEbus back-off 0us */
1220 #define TSI148_LCSR_DCTL_VBOT_1 (1<<8) /* VMEbus back-off 1us */
1221 #define TSI148_LCSR_DCTL_VBOT_2 (2<<8) /* VMEbus back-off 2us */
1222 #define TSI148_LCSR_DCTL_VBOT_4 (3<<8) /* VMEbus back-off 4us */
1223 #define TSI148_LCSR_DCTL_VBOT_8 (4<<8) /* VMEbus back-off 8us */
1224 #define TSI148_LCSR_DCTL_VBOT_16 (5<<8) /* VMEbus back-off 16us */
1225 #define TSI148_LCSR_DCTL_VBOT_32 (6<<8) /* VMEbus back-off 32us */
1226 #define TSI148_LCSR_DCTL_VBOT_64 (7<<8) /* VMEbus back-off 64us */
1239 #define TSI148_LCSR_DCTL_PBOT_0 (0<<0) /* PCI back off 0us */
1240 #define TSI148_LCSR_DCTL_PBOT_1 (1<<0) /* PCI back off 1us */
1241 #define TSI148_LCSR_DCTL_PBOT_2 (2<<0) /* PCI back off 2us */
1242 #define TSI148_LCSR_DCTL_PBOT_4 (3<<0) /* PCI back off 3us */
1243 #define TSI148_LCSR_DCTL_PBOT_8 (4<<0) /* PCI back off 4us */
1244 #define TSI148_LCSR_DCTL_PBOT_16 (5<<0) /* PCI back off 8us */
1245 #define TSI148_LCSR_DCTL_PBOT_32 (6<<0) /* PCI back off 16us */
1246 #define TSI148_LCSR_DCTL_PBOT_64 (7<<0) /* PCI back off 32us */