Lines Matching refs:iowrite32
189 iowrite32(serviced, bridge->base + LINT_STAT); in ca91cx42_irqhandler()
206 iowrite32(0, bridge->base + VINT_EN); in ca91cx42_irq_init()
209 iowrite32(0, bridge->base + LINT_EN); in ca91cx42_irq_init()
211 iowrite32(0x00FFFFFF, bridge->base + LINT_STAT); in ca91cx42_irq_init()
222 iowrite32(0, bridge->base + LINT_MAP0); in ca91cx42_irq_init()
223 iowrite32(0, bridge->base + LINT_MAP1); in ca91cx42_irq_init()
224 iowrite32(0, bridge->base + LINT_MAP2); in ca91cx42_irq_init()
231 iowrite32(tmp, bridge->base + LINT_EN); in ca91cx42_irq_init()
242 iowrite32(0, bridge->base + VINT_EN); in ca91cx42_irq_exit()
245 iowrite32(0, bridge->base + LINT_EN); in ca91cx42_irq_exit()
247 iowrite32(0x00FFFFFF, bridge->base + LINT_STAT); in ca91cx42_irq_exit()
287 iowrite32(tmp, bridge->base + LINT_EN); in ca91cx42_irq_set()
313 iowrite32(statid << 24, bridge->base + STATID); in ca91cx42_irq_generate()
317 iowrite32(tmp, bridge->base + VINT_EN); in ca91cx42_irq_generate()
326 iowrite32(tmp, bridge->base + VINT_EN); in ca91cx42_irq_generate()
406 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); in ca91cx42_slave_set()
409 iowrite32(vme_base, bridge->base + CA91CX42_VSI_BS[i]); in ca91cx42_slave_set()
410 iowrite32(vme_bound, bridge->base + CA91CX42_VSI_BD[i]); in ca91cx42_slave_set()
411 iowrite32(pci_offset, bridge->base + CA91CX42_VSI_TO[i]); in ca91cx42_slave_set()
429 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); in ca91cx42_slave_set()
434 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); in ca91cx42_slave_set()
652 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); in ca91cx42_master_set()
723 iowrite32(pci_base, bridge->base + CA91CX42_LSI_BS[i]); in ca91cx42_master_set()
724 iowrite32(pci_bound, bridge->base + CA91CX42_LSI_BD[i]); in ca91cx42_master_set()
725 iowrite32(vme_offset, bridge->base + CA91CX42_LSI_TO[i]); in ca91cx42_master_set()
728 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); in ca91cx42_master_set()
733 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); in ca91cx42_master_set()
943 iowrite32(*(u32 *)(buf + done), addr + done); in ca91cx42_master_write()
993 iowrite32(0, bridge->base + SCYC_CTL); in ca91cx42_master_rmw()
996 iowrite32(mask, bridge->base + SCYC_EN); in ca91cx42_master_rmw()
997 iowrite32(compare, bridge->base + SCYC_CMP); in ca91cx42_master_rmw()
998 iowrite32(swap, bridge->base + SCYC_SWP); in ca91cx42_master_rmw()
999 iowrite32(pci_addr, bridge->base + SCYC_ADDR); in ca91cx42_master_rmw()
1002 iowrite32(CA91CX42_SCYC_CTL_CYC_RMW, bridge->base + SCYC_CTL); in ca91cx42_master_rmw()
1008 iowrite32(0, bridge->base + SCYC_CTL); in ca91cx42_master_rmw()
1215 iowrite32(0, bridge->base + DTBC); in ca91cx42_dma_list_exec()
1216 iowrite32(bus_addr & ~CA91CX42_DCPP_M, bridge->base + DCPP); in ca91cx42_dma_list_exec()
1228 iowrite32(val, bridge->base + DGCS); in ca91cx42_dma_list_exec()
1232 iowrite32(val, bridge->base + DGCS); in ca91cx42_dma_list_exec()
1239 iowrite32(val | CA91CX42_DGCS_STOP_REQ, bridge->base + DGCS); in ca91cx42_dma_list_exec()
1350 iowrite32(lm_base, bridge->base + LM_BS); in ca91cx42_lm_set()
1351 iowrite32(lm_ctl, bridge->base + LM_CTL); in ca91cx42_lm_set()
1438 iowrite32(tmp, bridge->base + LINT_EN); in ca91cx42_lm_attach()
1443 iowrite32(lm_ctl, bridge->base + LM_CTL); in ca91cx42_lm_attach()
1466 iowrite32(tmp, bridge->base + LINT_EN); in ca91cx42_lm_detach()
1468 iowrite32(CA91CX42_LINT_LM[monitor], in ca91cx42_lm_detach()
1480 iowrite32(tmp, bridge->base + LM_CTL); in ca91cx42_lm_detach()
1548 iowrite32(geoid << 27, bridge->base + VCSR_BS); in ca91cx42_crcsr_init()
1567 iowrite32(bridge->crcsr_bus - crcsr_addr, bridge->base + VCSR_TO); in ca91cx42_crcsr_init()
1571 iowrite32(tmp, bridge->base + VCSR_CTL); in ca91cx42_crcsr_init()
1587 iowrite32(tmp, bridge->base + VCSR_CTL); in ca91cx42_crcsr_exit()
1590 iowrite32(0, bridge->base + VCSR_TO); in ca91cx42_crcsr_exit()
1857 iowrite32(0, bridge->base + LINT_EN); in ca91cx42_remove()
1860 iowrite32(0x00800000, bridge->base + LSI0_CTL); in ca91cx42_remove()
1861 iowrite32(0x00800000, bridge->base + LSI1_CTL); in ca91cx42_remove()
1862 iowrite32(0x00800000, bridge->base + LSI2_CTL); in ca91cx42_remove()
1863 iowrite32(0x00800000, bridge->base + LSI3_CTL); in ca91cx42_remove()
1864 iowrite32(0x00800000, bridge->base + LSI4_CTL); in ca91cx42_remove()
1865 iowrite32(0x00800000, bridge->base + LSI5_CTL); in ca91cx42_remove()
1866 iowrite32(0x00800000, bridge->base + LSI6_CTL); in ca91cx42_remove()
1867 iowrite32(0x00800000, bridge->base + LSI7_CTL); in ca91cx42_remove()
1868 iowrite32(0x00F00000, bridge->base + VSI0_CTL); in ca91cx42_remove()
1869 iowrite32(0x00F00000, bridge->base + VSI1_CTL); in ca91cx42_remove()
1870 iowrite32(0x00F00000, bridge->base + VSI2_CTL); in ca91cx42_remove()
1871 iowrite32(0x00F00000, bridge->base + VSI3_CTL); in ca91cx42_remove()
1872 iowrite32(0x00F00000, bridge->base + VSI4_CTL); in ca91cx42_remove()
1873 iowrite32(0x00F00000, bridge->base + VSI5_CTL); in ca91cx42_remove()
1874 iowrite32(0x00F00000, bridge->base + VSI6_CTL); in ca91cx42_remove()
1875 iowrite32(0x00F00000, bridge->base + VSI7_CTL); in ca91cx42_remove()