Lines Matching refs:ioread32
100 val = ioread32(bridge->base + DGCS); in ca91cx42_VERR_irqhandler()
117 val = ioread32(bridge->base + DGCS); in ca91cx42_LERR_irqhandler()
138 vec = ioread32(bridge->base + in ca91cx42_VIRQ_irqhandler()
160 enable = ioread32(bridge->base + LINT_EN); in ca91cx42_irqhandler()
161 stat = ioread32(bridge->base + LINT_STAT); in ca91cx42_irqhandler()
258 tmp = ioread32(bridge->base + LINT_STAT); in ca91cx42_iack_received()
280 tmp = ioread32(bridge->base + LINT_EN); in ca91cx42_irq_set()
310 tmp = ioread32(bridge->base + VINT_EN); in ca91cx42_irq_generate()
324 tmp = ioread32(bridge->base + VINT_EN); in ca91cx42_irq_generate()
404 temp_ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]); in ca91cx42_slave_set()
457 ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]); in ca91cx42_slave_get()
459 *vme_base = ioread32(bridge->base + CA91CX42_VSI_BS[i]); in ca91cx42_slave_get()
460 vme_bound = ioread32(bridge->base + CA91CX42_VSI_BD[i]); in ca91cx42_slave_get()
461 pci_offset = ioread32(bridge->base + CA91CX42_VSI_TO[i]); in ca91cx42_slave_get()
650 temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]); in ca91cx42_master_set()
758 ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]); in __ca91cx42_master_get()
760 pci_base = ioread32(bridge->base + CA91CX42_LSI_BS[i]); in __ca91cx42_master_get()
761 vme_offset = ioread32(bridge->base + CA91CX42_LSI_TO[i]); in __ca91cx42_master_get()
762 pci_bound = ioread32(bridge->base + CA91CX42_LSI_BD[i]); in __ca91cx42_master_get()
889 *(u32 *)(buf + done) = ioread32(addr + done); in ca91cx42_master_read()
1005 result = ioread32(image->kern_base + offset); in ca91cx42_master_rmw()
1169 tmp = ioread32(bridge->base + DGCS); in ca91cx42_dma_busy()
1219 val = ioread32(bridge->base + DGCS); in ca91cx42_dma_list_exec()
1238 val = ioread32(bridge->base + DGCS); in ca91cx42_dma_list_exec()
1251 val = ioread32(bridge->base + DGCS); in ca91cx42_dma_list_exec()
1257 val = ioread32(bridge->base + DCTL); in ca91cx42_dma_list_exec()
1371 *lm_base = (unsigned long long)ioread32(bridge->base + LM_BS); in ca91cx42_lm_get()
1372 lm_ctl = ioread32(bridge->base + LM_CTL); in ca91cx42_lm_get()
1417 lm_ctl = ioread32(bridge->base + LM_CTL); in ca91cx42_lm_attach()
1436 tmp = ioread32(bridge->base + LINT_EN); in ca91cx42_lm_attach()
1464 tmp = ioread32(bridge->base + LINT_EN); in ca91cx42_lm_detach()
1478 tmp = ioread32(bridge->base + LM_CTL); in ca91cx42_lm_detach()
1496 slot = ioread32(bridge->base + VCSR_BS); in ca91cx42_slot_get()
1569 tmp = ioread32(bridge->base + VCSR_CTL); in ca91cx42_crcsr_init()
1585 tmp = ioread32(bridge->base + VCSR_CTL); in ca91cx42_crcsr_exit()
1650 data = ioread32(ca91cx42_device->base + CA91CX42_PCI_ID) & 0x0000FFFF; in ca91cx42_probe()
1772 data = ioread32(ca91cx42_device->base + MISC_CTL); in ca91cx42_probe()