Lines Matching +full:0 +full:x10a0
20 #define mmCHIP_ID 0x0000
21 #define mmREVISION_ID 0x0004
22 #define mmWRAP_BUF_A 0x0008
23 #define mmWRAP_BUF_B 0x000C
24 #define mmWRAP_TOP_DIR 0x0010
25 #define mmWRAP_START_DIR 0x0014
26 #define mmCIF_CNTL 0x0018
27 #define mmCFGREG_BASE 0x001C
28 #define mmCIF_IO 0x0020
29 #define mmCIF_READ_DBG 0x0024
30 #define mmCIF_WRITE_DBG 0x0028
31 #define cfgIND_ADDR_A_0 0x0000
32 #define cfgIND_ADDR_A_1 0x0001
33 #define cfgIND_ADDR_A_2 0x0002
34 #define cfgIND_DATA_A 0x0003
35 #define cfgREG_BASE 0x0004
36 #define cfgINTF_CNTL 0x0005
37 #define cfgSTATUS 0x0006
38 #define cfgCPU_DEFAULTS 0x0007
39 #define cfgIND_ADDR_B_0 0x0008
40 #define cfgIND_ADDR_B_1 0x0009
41 #define cfgIND_ADDR_B_2 0x000A
42 #define cfgIND_DATA_B 0x000B
43 #define cfgPM4_RPTR 0x000C
44 #define cfgSCRATCH 0x000D
45 #define cfgPM4_WRPTR_0 0x000E
46 #define cfgPM4_WRPTR_1 0x000F
50 #define mmSCRATCH_UMSK 0x0280
51 #define mmSCRATCH_ADDR 0x0284
52 #define mmGEN_INT_CNTL 0x0200
53 #define mmGEN_INT_STATUS 0x0204
57 #define mmLCD_FORMAT 0x0410
58 #define mmGRAPHIC_CTRL 0x0414
59 #define mmGRAPHIC_OFFSET 0x0418
60 #define mmGRAPHIC_PITCH 0x041C
61 #define mmCRTC_TOTAL 0x0420
62 #define mmACTIVE_H_DISP 0x0424
63 #define mmACTIVE_V_DISP 0x0428
64 #define mmGRAPHIC_H_DISP 0x042C
65 #define mmGRAPHIC_V_DISP 0x0430
66 #define mmVIDEO_CTRL 0x0434
67 #define mmGRAPHIC_KEY 0x0438
68 #define mmBRIGHTNESS_CNTL 0x045C
69 #define mmDISP_INT_CNTL 0x0488
70 #define mmCRTC_SS 0x048C
71 #define mmCRTC_LS 0x0490
72 #define mmCRTC_REV 0x0494
73 #define mmCRTC_DCLK 0x049C
74 #define mmCRTC_GS 0x04A0
75 #define mmCRTC_VPOS_GS 0x04A4
76 #define mmCRTC_GCLK 0x04A8
77 #define mmCRTC_GOE 0x04AC
78 #define mmCRTC_FRAME 0x04B0
79 #define mmCRTC_FRAME_VPOS 0x04B4
80 #define mmGPIO_DATA 0x04B8
81 #define mmGPIO_CNTL1 0x04BC
82 #define mmGPIO_CNTL2 0x04C0
83 #define mmLCDD_CNTL1 0x04C4
84 #define mmLCDD_CNTL2 0x04C8
85 #define mmGENLCD_CNTL1 0x04CC
86 #define mmGENLCD_CNTL2 0x04D0
87 #define mmDISP_DEBUG 0x04D4
88 #define mmDISP_DB_BUF_CNTL 0x04D8
89 #define mmDISP_CRC_SIG 0x04DC
90 #define mmCRTC_DEFAULT_COUNT 0x04E0
91 #define mmLCD_BACKGROUND_COLOR 0x04E4
92 #define mmCRTC_PS2 0x04E8
93 #define mmCRTC_PS2_VPOS 0x04EC
94 #define mmCRTC_PS1_ACTIVE 0x04F0
95 #define mmCRTC_PS1_NACTIVE 0x04F4
96 #define mmCRTC_GCLK_EXT 0x04F8
97 #define mmCRTC_ALW 0x04FC
98 #define mmCRTC_ALW_VPOS 0x0500
99 #define mmCRTC_PSK 0x0504
100 #define mmCRTC_PSK_HPOS 0x0508
101 #define mmCRTC_CV4_START 0x050C
102 #define mmCRTC_CV4_END 0x0510
103 #define mmCRTC_CV4_HPOS 0x0514
104 #define mmCRTC_ECK 0x051C
105 #define mmREFRESH_CNTL 0x0520
106 #define mmGENLCD_CNTL3 0x0524
107 #define mmGPIO_DATA2 0x0528
108 #define mmGPIO_CNTL3 0x052C
109 #define mmGPIO_CNTL4 0x0530
110 #define mmCHIP_STRAP 0x0534
111 #define mmDISP_DEBUG2 0x0538
112 #define mmDEBUG_BUS_CNTL 0x053C
113 #define mmGAMMA_VALUE1 0x0540
114 #define mmGAMMA_VALUE2 0x0544
115 #define mmGAMMA_SLOPE 0x0548
116 #define mmGEN_STATUS 0x054C
117 #define mmHW_INT 0x0550
121 #define mmDST_OFFSET 0x1004
122 #define mmDST_PITCH 0x1008
123 #define mmDST_Y_X 0x1038
124 #define mmDST_WIDTH_HEIGHT 0x1198
125 #define mmDP_GUI_MASTER_CNTL 0x106C
126 #define mmBRUSH_OFFSET 0x108C
127 #define mmBRUSH_Y_X 0x1074
128 #define mmDP_BRUSH_FRGD_CLR 0x107C
129 #define mmSRC_OFFSET 0x11AC
130 #define mmSRC_PITCH 0x11B0
131 #define mmSRC_Y_X 0x1034
132 #define mmDEFAULT_PITCH_OFFSET 0x10A0
133 #define mmDEFAULT_SC_BOTTOM_RIGHT 0x10A8
134 #define mmDEFAULT2_SC_BOTTOM_RIGHT 0x10AC
135 #define mmSC_TOP_LEFT 0x11BC
136 #define mmSC_BOTTOM_RIGHT 0x11C0
137 #define mmSRC_SC_BOTTOM_RIGHT 0x11C4
138 #define mmGLOBAL_ALPHA 0x1210
139 #define mmFILTER_COEF 0x1214
140 #define mmMVC_CNTL_START 0x11E0
141 #define mmE2_ARITHMETIC_CNTL 0x1220
142 #define mmDP_CNTL 0x11C8
143 #define mmDP_CNTL_DST_DIR 0x11CC
144 #define mmDP_DATATYPE 0x12C4
145 #define mmDP_MIX 0x12C8
146 #define mmDP_WRITE_MSK 0x12CC
147 #define mmENG_CNTL 0x13E8
148 #define mmENG_PERF_CNT 0x13F0
152 #define mmIDCT_RUNS 0x0C00
153 #define mmIDCT_LEVELS 0x0C04
154 #define mmIDCT_CONTROL 0x0C3C
155 #define mmIDCT_AUTH_CONTROL 0x0C08
156 #define mmIDCT_AUTH 0x0C0C
160 #define mmMEM_CNTL 0x0180
161 #define mmMEM_ARB 0x0184
162 #define mmMC_FB_LOCATION 0x0188
163 #define mmMEM_EXT_CNTL 0x018C
164 #define mmMC_EXT_MEM_LOCATION 0x0190
165 #define mmMEM_EXT_TIMING_CNTL 0x0194
166 #define mmMEM_SDRAM_MODE_REG 0x0198
167 #define mmMEM_IO_CNTL 0x019C
168 #define mmMC_DEBUG 0x01A0
169 #define mmMC_BIST_CTRL 0x01A4
170 #define mmMC_BIST_COLLAR_READ 0x01A8
171 #define mmTC_MISMATCH 0x01AC
172 #define mmMC_PERF_MON_CNTL 0x01B0
173 #define mmMC_PERF_COUNTERS 0x01B4
177 #define mmBM_EXT_MEM_BANDWIDTH 0x0A00
178 #define mmBM_OFFSET 0x0A04
179 #define mmBM_MEM_EXT_TIMING_CNTL 0x0A08
180 #define mmBM_MEM_EXT_CNTL 0x0A0C
181 #define mmBM_MEM_MODE_REG 0x0A10
182 #define mmBM_MEM_IO_CNTL 0x0A18
183 #define mmBM_CONFIG 0x0A1C
184 #define mmBM_STATUS 0x0A20
185 #define mmBM_DEBUG 0x0A24
186 #define mmBM_PERF_MON_CNTL 0x0A28
187 #define mmBM_PERF_COUNTERS 0x0A2C
188 #define mmBM_PERF2_MON_CNTL 0x0A30
189 #define mmBM_PERF2_COUNTERS 0x0A34
193 #define mmWAIT_UNTIL 0x1400
194 #define mmISYNC_CNTL 0x1404
195 #define mmRBBM_STATUS 0x0140
196 #define mmRBBM_CNTL 0x0144
197 #define mmNQWAIT_UNTIL 0x0150
201 #define mmCLK_PIN_CNTL 0x0080
202 #define mmPLL_REF_FB_DIV 0x0084
203 #define mmPLL_CNTL 0x0088
204 #define mmSCLK_CNTL 0x008C
205 #define mmPCLK_CNTL 0x0090
206 #define mmCLK_TEST_CNTL 0x0094
207 #define mmPWRMGT_CNTL 0x0098
208 #define mmPWRMGT_STATUS 0x009C
212 #define defWRAP_TOP_DIR 0x00000000
213 #define defWRAP_START_DIR 0x00000000
214 #define defCFGREG_BASE 0x00000000
215 #define defCIF_IO 0x000C0902
216 #define defINTF_CNTL 0x00000011
217 #define defCPU_DEFAULTS 0x00000006
218 #define defHW_INT 0x00000000
219 #define defMC_EXT_MEM_LOCATION 0x07ff0000
220 #define defTC_MISMATCH 0x00000000
222 #define W100_CFG_BASE 0x0
223 #define W100_CFG_LEN 0x10
224 #define W100_REG_BASE 0x10000
225 #define W100_REG_LEN 0x2000
226 #define MEM_INT_BASE_VALUE 0x100000
227 #define MEM_EXT_BASE_VALUE 0x800000
228 #define MEM_INT_SIZE 0x05ffff
229 #define MEM_WINDOW_BASE 0x100000
230 #define MEM_WINDOW_SIZE 0xf00000
232 #define WRAP_BUF_BASE_VALUE 0x80000
233 #define WRAP_BUF_TOP_VALUE 0xbffff
235 #define CHIP_ID_W100 0x57411002
236 #define CHIP_ID_W3200 0x56441002
237 #define CHIP_ID_W3220 0x57441002
745 #define TESTCLK_SRC_PLL 0x01
746 #define TESTCLK_SRC_SCLK 0x02
747 #define TESTCLK_SRC_PCLK 0x03
749 #define TESTCLK_SRC_XTAL 0x06
785 #define ROP3_SRCCOPY 0xcc
786 #define ROP3_PATCOPY 0xf0
793 #define DP_OP_ROP 0