Lines Matching refs:io_register
343 struct io_register { struct
356 struct io_register reg[IGA2_SHADOW_HOR_TOTAL_REG_NUM]; argument
362 struct io_register reg[IGA2_SHADOW_HOR_BLANK_END_REG_NUM];
368 struct io_register reg[IGA2_SHADOW_VER_TOTAL_REG_NUM];
374 struct io_register reg[IGA2_SHADOW_VER_ADDR_REG_NUM];
380 struct io_register reg[IGA2_SHADOW_VER_BLANK_START_REG_NUM];
386 struct io_register reg[IGA2_SHADOW_VER_BLANK_END_REG_NUM];
392 struct io_register reg[IGA2_SHADOW_VER_SYNC_START_REG_NUM];
398 struct io_register reg[IGA2_SHADOW_VER_SYNC_END_REG_NUM];
404 struct io_register reg[IGA1_FETCH_COUNT_REG_NUM];
410 struct io_register reg[IGA2_FETCH_COUNT_REG_NUM];
421 struct io_register reg[IGA1_STARTING_ADDR_REG_NUM];
426 struct io_register reg[IGA2_STARTING_ADDR_REG_NUM];
437 struct io_register reg[LCD_POWER_SEQ_TD0_REG_NUM];
442 struct io_register reg[LCD_POWER_SEQ_TD1_REG_NUM];
447 struct io_register reg[LCD_POWER_SEQ_TD2_REG_NUM];
452 struct io_register reg[LCD_POWER_SEQ_TD3_REG_NUM];
465 struct io_register reg[LCD_HOR_SCALING_FACTOR_REG_NUM];
470 struct io_register reg[LCD_VER_SCALING_FACTOR_REG_NUM];
501 struct io_register reg[IGA1_FIFO_DEPTH_SELECT_REG_NUM];
506 struct io_register reg[IGA1_FIFO_THRESHOLD_REG_NUM];
511 struct io_register reg[IGA1_FIFO_HIGH_THRESHOLD_REG_NUM];
516 struct io_register reg[IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];
521 struct io_register reg[IGA2_FIFO_DEPTH_SELECT_REG_NUM];
526 struct io_register reg[IGA2_FIFO_THRESHOLD_REG_NUM];
531 struct io_register reg[IGA2_FIFO_HIGH_THRESHOLD_REG_NUM];
536 struct io_register reg[IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];
632 struct io_register *reg,