Lines Matching +full:0 +full:x000002a0
65 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || in nv3Busy()
66 NV_RD32(&chip->PGRAPH[0x000006B0/4], 0) & 0x01); in nv3Busy()
73 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || in nv4Busy()
74 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01); in nv4Busy()
81 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || in nv10Busy()
82 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01); in nv10Busy()
92 VGA_WR08(chip->PCIO, 0x3D4, 0x11); in vgaLockUnlock()
93 cr11 = VGA_RD08(chip->PCIO, 0x3D5); in vgaLockUnlock()
94 if(Lock) cr11 |= 0x80; in vgaLockUnlock()
95 else cr11 &= ~0x80; in vgaLockUnlock()
96 VGA_WR08(chip->PCIO, 0x3D5, cr11); in vgaLockUnlock()
104 VGA_WR08(chip->PVIO, 0x3C4, 0x06); in nv3LockUnlock()
105 VGA_WR08(chip->PVIO, 0x3C5, Lock ? 0x99 : 0x57); in nv3LockUnlock()
114 VGA_WR08(chip->PCIO, 0x3D4, 0x1F); in nv4LockUnlock()
115 VGA_WR08(chip->PCIO, 0x3D5, Lock ? 0x99 : 0x57); in nv4LockUnlock()
127 chip->CurrentState->cursor1 = (chip->CurrentState->cursor1 & 0xFE) | in ShowHideCursor()
128 (ShowHide & 0x01); in ShowHideCursor()
129 VGA_WR08(chip->PCIO, 0x3D4, 0x31); in ShowHideCursor()
130 VGA_WR08(chip->PCIO, 0x3D5, chip->CurrentState->cursor1); in ShowHideCursor()
131 return (cursor & 0x01); in ShowHideCursor()
146 #define VIDEO 0
244 int iter = 0; in nv3_iterate()
255 vlwm = 0; in nv3_iterate()
256 glwm = 0; in nv3_iterate()
257 mlwm = 0; in nv3_iterate()
258 vfsize = 0; in nv3_iterate()
259 gfsize = 0; in nv3_iterate()
289 mfsize = 0; in nv3_iterate()
291 if (ainfo->vid_en && (ainfo->vocc < 0) && !ainfo->vid_only_once) in nv3_iterate()
293 else if (ainfo->mocc < 0) in nv3_iterate()
297 else return (0); in nv3_iterate()
301 if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once) in nv3_iterate()
303 else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once) in nv3_iterate()
305 else if (ainfo->mocc<0) in nv3_iterate()
307 else return (0); in nv3_iterate()
310 if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once) in nv3_iterate()
312 else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once) in nv3_iterate()
314 else if (ainfo->mocc<0) in nv3_iterate()
316 else return (0); in nv3_iterate()
319 if (ainfo->mocc<0) in nv3_iterate()
321 else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once) in nv3_iterate()
323 else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once) in nv3_iterate()
325 else return (0); in nv3_iterate()
334 if (last==cur) misses = 0; in nv3_iterate()
337 ainfo->first_vacc = 0; in nv3_iterate()
350 if (last==cur) misses = 0; in nv3_iterate()
353 ainfo->first_gacc = 0; in nv3_iterate()
361 ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000; in nv3_iterate()
363 ainfo->mocc = ainfo->mocc + 0 - ns*ainfo->mdrain_rate/1000000; in nv3_iterate()
366 if (last==cur) misses = 0; in nv3_iterate()
369 ainfo->first_macc = 0; in nv3_iterate()
371 ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000; in nv3_iterate()
372 ainfo->gocc = ainfo->gocc + 0 - ns*ainfo->gdrain_rate/1000000; in nv3_iterate()
378 ainfo->converged = 0; in nv3_iterate()
383 if (abs(ainfo->gburst_size) + ((abs(ainfo->wcglwm) + 16 ) & ~0x7) - tmp > max_gfsize) in nv3_iterate()
385 ainfo->converged = 0; in nv3_iterate()
390 if (abs(ainfo->vburst_size) + (abs(ainfo->wcvlwm + 32) & ~0xf) - tmp> VFIFO_SIZE) in nv3_iterate()
392 ainfo->converged = 0; in nv3_iterate()
397 ainfo->converged = 0; in nv3_iterate()
402 ainfo->converged = 0; in nv3_iterate()
407 ainfo->converged = 0; in nv3_iterate()
412 ainfo->converged = 0; in nv3_iterate()
417 ainfo->converged = 0; in nv3_iterate()
422 ainfo->converged = 0; in nv3_iterate()
442 ainfo->wcmocc = 0; in nv3_arb()
443 ainfo->wcgocc = 0; in nv3_arb()
444 ainfo->wcvocc = 0; in nv3_arb()
445 ainfo->wcvlwm = 0; in nv3_arb()
446 ainfo->wcglwm = 0; in nv3_arb()
452 ainfo->mocc = state->enable_mp ? 0-ens*ainfo->mdrain_rate/1000000 : 0; in nv3_arb()
453 ainfo->vocc = ainfo->vid_en ? 0-ens*ainfo->vdrain_rate/1000000 : 0; in nv3_arb()
454 ainfo->gocc = ainfo->gr_en ? 0-ens*ainfo->gdrain_rate/1000000 : 0; in nv3_arb()
464 ainfo->mocc = state->enable_mp ? 0 : mburst_size - mns*ainfo->mdrain_rate/1000000; in nv3_arb()
465 ainfo->vocc = ainfo->vid_en ? 0 : 0- mns*ainfo->vdrain_rate/1000000; in nv3_arb()
466 ainfo->gocc = ainfo->gr_en ? 0: 0- mns*ainfo->gdrain_rate/1000000; in nv3_arb()
470 ainfo->first_macc = 0; in nv3_arb()
476 ainfo->first_gacc = 0; in nv3_arb()
480 ainfo->vocc = ainfo->vid_en? 0-gns*ainfo->vdrain_rate/1000000 : 0; in nv3_arb()
481 ainfo->mocc = state->enable_mp ? 0-gns*ainfo->mdrain_rate/1000000: 0; in nv3_arb()
487 ainfo->first_vacc = 0; in nv3_arb()
492 ainfo->gocc = ainfo->gr_en? (0-vns*ainfo->gdrain_rate/1000000) : 0; in nv3_arb()
493 ainfo->mocc = state->enable_mp? 0-vns*ainfo->mdrain_rate/1000000 :0 ; in nv3_arb()
511 res_info->graphics_hi_priority = 0; in nv3_arb()
512 res_info->media_hi_priority = 0; in nv3_arb()
513 ainfo->converged = 0; in nv3_arb()
514 return (0); in nv3_arb()
528 res_info->graphics_hi_priority = 0; in nv3_arb()
529 res_info->media_hi_priority = 0; in nv3_arb()
530 return (0); in nv3_arb()
537 done = 0; in nv3_get_param()
538 for (p=0; p < 2; p++) in nv3_get_param()
550 done = 0; in nv3_get_param()
572 ainfo.vid_only_once = 0; in nv3CalcArbitration()
573 ainfo.gr_only_once = 0; in nv3CalcArbitration()
576 if (state->video_scale != 0) in nv3CalcArbitration()
579 res_info->rtl_values = 0; in nv3CalcArbitration()
584 ainfo.gdrain_rate = 0; in nv3CalcArbitration()
593 ainfo.vdrain_rate = 0; in nv3CalcArbitration()
602 if (!ainfo.gr_en) ainfo.gdrain_rate = 0; in nv3CalcArbitration()
603 if (!ainfo.vid_en) ainfo.vdrain_rate = 0; in nv3CalcArbitration()
621 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); in nv3UpdateArbitrationSettings()
622 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; in nv3UpdateArbitrationSettings()
625 sim_data.enable_video = 0; in nv3UpdateArbitrationSettings()
626 sim_data.enable_mp = 0; in nv3UpdateArbitrationSettings()
628 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? in nv3UpdateArbitrationSettings()
635 sim_data.gr_during_vid = 0; in nv3UpdateArbitrationSettings()
642 *burst = 0; in nv3UpdateArbitrationSettings()
649 *lwm = 0x24; in nv3UpdateArbitrationSettings()
650 *burst = 0x2; in nv3UpdateArbitrationSettings()
679 clwm = 0; in nv4CalcArbitration()
680 vlwm = 0; in nv4CalcArbitration()
701 nvclks += 0; in nv4CalcArbitration()
702 pclks += 0; in nv4CalcArbitration()
703 found = 0; in nv4CalcArbitration()
704 vbs = 0; in nv4CalcArbitration()
758 if ((p1 < m1) && (m1 > 0)) in nv4CalcArbitration()
760 fifo->valid = 0; in nv4CalcArbitration()
761 found = 0; in nv4CalcArbitration()
762 if (mclk_extra ==0) found = 1; in nv4CalcArbitration()
769 fifo->valid = 0; in nv4CalcArbitration()
770 found = 0; in nv4CalcArbitration()
771 if (mclk_extra ==0) found = 1; in nv4CalcArbitration()
779 fifo->valid = 0; in nv4CalcArbitration()
780 found = 0; in nv4CalcArbitration()
781 if (mclk_extra ==0) found = 1; in nv4CalcArbitration()
810 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); in nv4UpdateArbitrationSettings()
811 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; in nv4UpdateArbitrationSettings()
813 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); in nv4UpdateArbitrationSettings()
814 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; in nv4UpdateArbitrationSettings()
816 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0); in nv4UpdateArbitrationSettings()
818 sim_data.enable_video = 0; in nv4UpdateArbitrationSettings()
819 sim_data.enable_mp = 0; in nv4UpdateArbitrationSettings()
820 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? in nv4UpdateArbitrationSettings()
822 sim_data.mem_latency = (char)cfg1 & 0x0F; in nv4UpdateArbitrationSettings()
824 sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01)); in nv4UpdateArbitrationSettings()
825 sim_data.gr_during_vid = 0; in nv4UpdateArbitrationSettings()
833 *burst = 0; in nv4UpdateArbitrationSettings()
870 clwm = 0; in nv10CalcArbitration()
891 if (arb->memory_type == 0) in nv10CalcArbitration()
923 nvclks += 0; in nv10CalcArbitration()
924 pclks += 0; in nv10CalcArbitration()
925 found = 0; in nv10CalcArbitration()
937 us_extra = 0; in nv10CalcArbitration()
941 vus_p = 0*1000*1000 / pclk_freq;/* pclk latency in us */ in nv10CalcArbitration()
999 clwm = 0xfff; /*Large number to fail */ in nv10CalcArbitration()
1027 if((p2 < m1) && (m1 > 0)) { in nv10CalcArbitration()
1028 fifo->valid = 0; in nv10CalcArbitration()
1029 found = 0; in nv10CalcArbitration()
1030 if(min_mclk_extra == 0) { in nv10CalcArbitration()
1041 fifo->valid = 0; in nv10CalcArbitration()
1042 found = 0; in nv10CalcArbitration()
1043 if(min_mclk_extra == 0) in nv10CalcArbitration()
1053 /* printf("CRT LWM: %f bytes, prog: 0x%x, bs: 256\n", clwm, data ); */ in nv10CalcArbitration()
1056 /* printf("VID LWM: %f bytes, prog: 0x%x, bs: %d\n, ", vlwm, data, vbs ); */ in nv10CalcArbitration()
1073 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); in nv10UpdateArbitrationSettings()
1074 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; in nv10UpdateArbitrationSettings()
1076 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); in nv10UpdateArbitrationSettings()
1077 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; in nv10UpdateArbitrationSettings()
1079 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0); in nv10UpdateArbitrationSettings()
1081 sim_data.enable_video = 0; in nv10UpdateArbitrationSettings()
1082 sim_data.enable_mp = 0; in nv10UpdateArbitrationSettings()
1083 sim_data.memory_type = (NV_RD32(&chip->PFB[0x00000200/4], 0) & 0x01) ? in nv10UpdateArbitrationSettings()
1084 1 : 0; in nv10UpdateArbitrationSettings()
1085 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? in nv10UpdateArbitrationSettings()
1087 sim_data.mem_latency = (char)cfg1 & 0x0F; in nv10UpdateArbitrationSettings()
1089 sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01)); in nv10UpdateArbitrationSettings()
1090 sim_data.gr_during_vid = 0; in nv10UpdateArbitrationSettings()
1098 *burst = 0; in nv10UpdateArbitrationSettings()
1122 dev = pci_get_domain_bus_and_slot(domain, 0, 3); in nForceUpdateArbitrationSettings()
1123 pci_read_config_dword(dev, 0x6C, &uMClkPostDiv); in nForceUpdateArbitrationSettings()
1125 uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf; in nForceUpdateArbitrationSettings()
1130 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); in nForceUpdateArbitrationSettings()
1131 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; in nForceUpdateArbitrationSettings()
1134 sim_data.enable_video = 0; in nForceUpdateArbitrationSettings()
1135 sim_data.enable_mp = 0; in nForceUpdateArbitrationSettings()
1137 dev = pci_get_domain_bus_and_slot(domain, 0, 1); in nForceUpdateArbitrationSettings()
1138 pci_read_config_dword(dev, 0x7C, &sim_data.memory_type); in nForceUpdateArbitrationSettings()
1146 sim_data.gr_during_vid = 0; in nForceUpdateArbitrationSettings()
1154 *burst = 0; in nForceUpdateArbitrationSettings()
1185 DeltaOld = 0xFFFFFFFF; in CalcVClock()
1201 for (P = 0; P <= highP; P ++) in CalcVClock()
1229 return (DeltaOld != 0xFFFFFFFF); in CalcVClock()
1271 state->cursor0 = 0x00; in CalcStateExt()
1272 state->cursor1 = 0x78; in CalcStateExt()
1273 state->cursor2 = 0x00000000; in CalcStateExt()
1274 state->pllsel = 0x10010100; in CalcStateExt()
1277 | 0x1000; in CalcStateExt()
1278 state->general = 0x00100100; in CalcStateExt()
1279 state->repaint1 = hDisplaySize < 1280 ? 0x06 : 0x02; in CalcStateExt()
1287 state->cursor0 = 0x00; in CalcStateExt()
1288 state->cursor1 = 0xFC; in CalcStateExt()
1289 state->cursor2 = 0x00000000; in CalcStateExt()
1290 state->pllsel = 0x10000700; in CalcStateExt()
1291 state->config = 0x00001114; in CalcStateExt()
1292 state->general = bpp == 16 ? 0x00101100 : 0x00100100; in CalcStateExt()
1293 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00; in CalcStateExt()
1313 state->cursor0 = 0x80 | (chip->CursorStart >> 17); in CalcStateExt()
1316 state->pllsel = 0x10000700; in CalcStateExt()
1317 state->config = NV_RD32(&chip->PFB[0x00000200/4], 0); in CalcStateExt()
1318 state->general = bpp == 16 ? 0x00101100 : 0x00100100; in CalcStateExt()
1319 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00; in CalcStateExt()
1326 state->general |= 0x00000030; in CalcStateExt()
1329 state->repaint0 = (((width/8)*pixelDepth) & 0x700) >> 3; in CalcStateExt()
1334 state->offset3 = 0; in CalcStateExt()
1340 return 0; in CalcStateExt()
1346 for (i = 0; i < sizeof(tbl##Table##dev)/8; i++) \
1347 NV_WR32(&chip->dev[tbl##Table##dev[i][0]], 0, tbl##Table##dev[i][1])
1349 for (i = 0; i < sizeof(tbl##Table##dev##_8BPP)/8; i++) \
1350 NV_WR32(&chip->dev[tbl##Table##dev##_8BPP[i][0]], 0, tbl##Table##dev##_8BPP[i][1])
1352 for (i = 0; i < sizeof(tbl##Table##dev##_15BPP)/8; i++) \
1353 NV_WR32(&chip->dev[tbl##Table##dev##_15BPP[i][0]], 0, tbl##Table##dev##_15BPP[i][1])
1355 for (i = 0; i < sizeof(tbl##Table##dev##_16BPP)/8; i++) \
1356 NV_WR32(&chip->dev[tbl##Table##dev##_16BPP[i][0]], 0, tbl##Table##dev##_16BPP[i][1])
1358 for (i = 0; i < sizeof(tbl##Table##dev##_32BPP)/8; i++) \
1359 NV_WR32(&chip->dev[tbl##Table##dev##_32BPP[i][0]], 0, tbl##Table##dev##_32BPP[i][1])
1373 chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]); in UpdateFifoState()
1384 chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]); in UpdateFifoState()
1407 NV_WR32(chip->PFB, 0x00000200, state->config); in LoadStateExt()
1417 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); in LoadStateExt()
1432 for (i = 0x00000; i < 0x00800; i++) in LoadStateExt()
1433 NV_WR32(&chip->PRAMIN[0x00000502 + i], 0, (i << 12) | 0x03); in LoadStateExt()
1434 NV_WR32(chip->PGRAPH, 0x00000630, state->offset0); in LoadStateExt()
1435 NV_WR32(chip->PGRAPH, 0x00000634, state->offset1); in LoadStateExt()
1436 NV_WR32(chip->PGRAPH, 0x00000638, state->offset2); in LoadStateExt()
1437 NV_WR32(chip->PGRAPH, 0x0000063C, state->offset3); in LoadStateExt()
1438 NV_WR32(chip->PGRAPH, 0x00000650, state->pitch0); in LoadStateExt()
1439 NV_WR32(chip->PGRAPH, 0x00000654, state->pitch1); in LoadStateExt()
1440 NV_WR32(chip->PGRAPH, 0x00000658, state->pitch2); in LoadStateExt()
1441 NV_WR32(chip->PGRAPH, 0x0000065C, state->pitch3); in LoadStateExt()
1447 NV_WR32(chip->PFB, 0x00000200, state->config); in LoadStateExt()
1456 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); in LoadStateExt()
1461 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); in LoadStateExt()
1476 NV_WR32(chip->PGRAPH, 0x00000640, state->offset0); in LoadStateExt()
1477 NV_WR32(chip->PGRAPH, 0x00000644, state->offset1); in LoadStateExt()
1478 NV_WR32(chip->PGRAPH, 0x00000648, state->offset2); in LoadStateExt()
1479 NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3); in LoadStateExt()
1480 NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0); in LoadStateExt()
1481 NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1); in LoadStateExt()
1482 NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2); in LoadStateExt()
1483 NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3); in LoadStateExt()
1489 VGA_WR08(chip->PCIO, 0x03D4, 0x44); in LoadStateExt()
1490 VGA_WR08(chip->PCIO, 0x03D5, state->crtcOwner); in LoadStateExt()
1491 chip->LockUnlock(chip, 0); in LoadStateExt()
1502 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); in LoadStateExt()
1507 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); in LoadStateExt()
1524 NV_WR32(chip->PGRAPH, 0x00000640, state->offset0); in LoadStateExt()
1525 NV_WR32(chip->PGRAPH, 0x00000644, state->offset1); in LoadStateExt()
1526 NV_WR32(chip->PGRAPH, 0x00000648, state->offset2); in LoadStateExt()
1527 NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3); in LoadStateExt()
1528 NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0); in LoadStateExt()
1529 NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1); in LoadStateExt()
1530 NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2); in LoadStateExt()
1531 NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3); in LoadStateExt()
1532 NV_WR32(chip->PGRAPH, 0x00000680, state->pitch3); in LoadStateExt()
1534 NV_WR32(chip->PGRAPH, 0x00000820, state->offset0); in LoadStateExt()
1535 NV_WR32(chip->PGRAPH, 0x00000824, state->offset1); in LoadStateExt()
1536 NV_WR32(chip->PGRAPH, 0x00000828, state->offset2); in LoadStateExt()
1537 NV_WR32(chip->PGRAPH, 0x0000082C, state->offset3); in LoadStateExt()
1538 NV_WR32(chip->PGRAPH, 0x00000850, state->pitch0); in LoadStateExt()
1539 NV_WR32(chip->PGRAPH, 0x00000854, state->pitch1); in LoadStateExt()
1540 NV_WR32(chip->PGRAPH, 0x00000858, state->pitch2); in LoadStateExt()
1541 NV_WR32(chip->PGRAPH, 0x0000085C, state->pitch3); in LoadStateExt()
1542 NV_WR32(chip->PGRAPH, 0x00000860, state->pitch3); in LoadStateExt()
1543 NV_WR32(chip->PGRAPH, 0x00000864, state->pitch3); in LoadStateExt()
1544 NV_WR32(chip->PGRAPH, 0x000009A4, NV_RD32(chip->PFB, 0x00000200)); in LoadStateExt()
1545 NV_WR32(chip->PGRAPH, 0x000009A8, NV_RD32(chip->PFB, 0x00000204)); in LoadStateExt()
1548 NV_WR32(chip->PCRTC0, 0x00000860, state->head); in LoadStateExt()
1549 NV_WR32(chip->PCRTC0, 0x00002860, state->head2); in LoadStateExt()
1551 NV_WR32(chip->PRAMDAC, 0x00000404, NV_RD32(chip->PRAMDAC, 0x00000404) | (1 << 25)); in LoadStateExt()
1553 NV_WR32(chip->PMC, 0x00008704, 1); in LoadStateExt()
1554 NV_WR32(chip->PMC, 0x00008140, 0); in LoadStateExt()
1555 NV_WR32(chip->PMC, 0x00008920, 0); in LoadStateExt()
1556 NV_WR32(chip->PMC, 0x00008924, 0); in LoadStateExt()
1557 NV_WR32(chip->PMC, 0x00008908, 0x01ffffff); in LoadStateExt()
1558 NV_WR32(chip->PMC, 0x0000890C, 0x01ffffff); in LoadStateExt()
1559 NV_WR32(chip->PMC, 0x00001588, 0); in LoadStateExt()
1561 NV_WR32(chip->PFB, 0x00000240, 0); in LoadStateExt()
1562 NV_WR32(chip->PFB, 0x00000250, 0); in LoadStateExt()
1563 NV_WR32(chip->PFB, 0x00000260, 0); in LoadStateExt()
1564 NV_WR32(chip->PFB, 0x00000270, 0); in LoadStateExt()
1565 NV_WR32(chip->PFB, 0x00000280, 0); in LoadStateExt()
1566 NV_WR32(chip->PFB, 0x00000290, 0); in LoadStateExt()
1567 NV_WR32(chip->PFB, 0x000002A0, 0); in LoadStateExt()
1568 NV_WR32(chip->PFB, 0x000002B0, 0); in LoadStateExt()
1570 NV_WR32(chip->PGRAPH, 0x00000B00, NV_RD32(chip->PFB, 0x00000240)); in LoadStateExt()
1571 NV_WR32(chip->PGRAPH, 0x00000B04, NV_RD32(chip->PFB, 0x00000244)); in LoadStateExt()
1572 NV_WR32(chip->PGRAPH, 0x00000B08, NV_RD32(chip->PFB, 0x00000248)); in LoadStateExt()
1573 NV_WR32(chip->PGRAPH, 0x00000B0C, NV_RD32(chip->PFB, 0x0000024C)); in LoadStateExt()
1574 NV_WR32(chip->PGRAPH, 0x00000B10, NV_RD32(chip->PFB, 0x00000250)); in LoadStateExt()
1575 NV_WR32(chip->PGRAPH, 0x00000B14, NV_RD32(chip->PFB, 0x00000254)); in LoadStateExt()
1576 NV_WR32(chip->PGRAPH, 0x00000B18, NV_RD32(chip->PFB, 0x00000258)); in LoadStateExt()
1577 NV_WR32(chip->PGRAPH, 0x00000B1C, NV_RD32(chip->PFB, 0x0000025C)); in LoadStateExt()
1578 NV_WR32(chip->PGRAPH, 0x00000B20, NV_RD32(chip->PFB, 0x00000260)); in LoadStateExt()
1579 NV_WR32(chip->PGRAPH, 0x00000B24, NV_RD32(chip->PFB, 0x00000264)); in LoadStateExt()
1580 NV_WR32(chip->PGRAPH, 0x00000B28, NV_RD32(chip->PFB, 0x00000268)); in LoadStateExt()
1581 NV_WR32(chip->PGRAPH, 0x00000B2C, NV_RD32(chip->PFB, 0x0000026C)); in LoadStateExt()
1582 NV_WR32(chip->PGRAPH, 0x00000B30, NV_RD32(chip->PFB, 0x00000270)); in LoadStateExt()
1583 NV_WR32(chip->PGRAPH, 0x00000B34, NV_RD32(chip->PFB, 0x00000274)); in LoadStateExt()
1584 NV_WR32(chip->PGRAPH, 0x00000B38, NV_RD32(chip->PFB, 0x00000278)); in LoadStateExt()
1585 NV_WR32(chip->PGRAPH, 0x00000B3C, NV_RD32(chip->PFB, 0x0000027C)); in LoadStateExt()
1586 NV_WR32(chip->PGRAPH, 0x00000B40, NV_RD32(chip->PFB, 0x00000280)); in LoadStateExt()
1587 NV_WR32(chip->PGRAPH, 0x00000B44, NV_RD32(chip->PFB, 0x00000284)); in LoadStateExt()
1588 NV_WR32(chip->PGRAPH, 0x00000B48, NV_RD32(chip->PFB, 0x00000288)); in LoadStateExt()
1589 NV_WR32(chip->PGRAPH, 0x00000B4C, NV_RD32(chip->PFB, 0x0000028C)); in LoadStateExt()
1590 NV_WR32(chip->PGRAPH, 0x00000B50, NV_RD32(chip->PFB, 0x00000290)); in LoadStateExt()
1591 NV_WR32(chip->PGRAPH, 0x00000B54, NV_RD32(chip->PFB, 0x00000294)); in LoadStateExt()
1592 NV_WR32(chip->PGRAPH, 0x00000B58, NV_RD32(chip->PFB, 0x00000298)); in LoadStateExt()
1593 NV_WR32(chip->PGRAPH, 0x00000B5C, NV_RD32(chip->PFB, 0x0000029C)); in LoadStateExt()
1594 NV_WR32(chip->PGRAPH, 0x00000B60, NV_RD32(chip->PFB, 0x000002A0)); in LoadStateExt()
1595 NV_WR32(chip->PGRAPH, 0x00000B64, NV_RD32(chip->PFB, 0x000002A4)); in LoadStateExt()
1596 NV_WR32(chip->PGRAPH, 0x00000B68, NV_RD32(chip->PFB, 0x000002A8)); in LoadStateExt()
1597 NV_WR32(chip->PGRAPH, 0x00000B6C, NV_RD32(chip->PFB, 0x000002AC)); in LoadStateExt()
1598 NV_WR32(chip->PGRAPH, 0x00000B70, NV_RD32(chip->PFB, 0x000002B0)); in LoadStateExt()
1599 NV_WR32(chip->PGRAPH, 0x00000B74, NV_RD32(chip->PFB, 0x000002B4)); in LoadStateExt()
1600 NV_WR32(chip->PGRAPH, 0x00000B78, NV_RD32(chip->PFB, 0x000002B8)); in LoadStateExt()
1601 NV_WR32(chip->PGRAPH, 0x00000B7C, NV_RD32(chip->PFB, 0x000002BC)); in LoadStateExt()
1602 NV_WR32(chip->PGRAPH, 0x00000F40, 0x10000000); in LoadStateExt()
1603 NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000000); in LoadStateExt()
1604 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040); in LoadStateExt()
1605 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000008); in LoadStateExt()
1606 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000200); in LoadStateExt()
1607 for (i = 0; i < (3*16); i++) in LoadStateExt()
1608 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1609 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040); in LoadStateExt()
1610 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1611 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000800); in LoadStateExt()
1612 for (i = 0; i < (16*16); i++) in LoadStateExt()
1613 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1614 NV_WR32(chip->PGRAPH, 0x00000F40, 0x30000000); in LoadStateExt()
1615 NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000004); in LoadStateExt()
1616 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006400); in LoadStateExt()
1617 for (i = 0; i < (59*4); i++) in LoadStateExt()
1618 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1619 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006800); in LoadStateExt()
1620 for (i = 0; i < (47*4); i++) in LoadStateExt()
1621 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1622 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006C00); in LoadStateExt()
1623 for (i = 0; i < (3*4); i++) in LoadStateExt()
1624 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1625 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007000); in LoadStateExt()
1626 for (i = 0; i < (19*4); i++) in LoadStateExt()
1627 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1628 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007400); in LoadStateExt()
1629 for (i = 0; i < (12*4); i++) in LoadStateExt()
1630 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1631 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007800); in LoadStateExt()
1632 for (i = 0; i < (12*4); i++) in LoadStateExt()
1633 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1634 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00004400); in LoadStateExt()
1635 for (i = 0; i < (8*4); i++) in LoadStateExt()
1636 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1637 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000000); in LoadStateExt()
1638 for (i = 0; i < 16; i++) in LoadStateExt()
1639 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1640 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040); in LoadStateExt()
1641 for (i = 0; i < 4; i++) in LoadStateExt()
1642 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1644 NV_WR32(chip->PCRTC, 0x00000810, state->cursorConfig); in LoadStateExt()
1647 if((chip->Chipset & 0x0ff0) == 0x0110) { in LoadStateExt()
1648 NV_WR32(chip->PRAMDAC, 0x0528, state->dither); in LoadStateExt()
1650 if((chip->Chipset & 0x0ff0) >= 0x0170) { in LoadStateExt()
1651 NV_WR32(chip->PRAMDAC, 0x083C, state->dither); in LoadStateExt()
1654 VGA_WR08(chip->PCIO, 0x03D4, 0x53); in LoadStateExt()
1655 VGA_WR08(chip->PCIO, 0x03D5, 0); in LoadStateExt()
1656 VGA_WR08(chip->PCIO, 0x03D4, 0x54); in LoadStateExt()
1657 VGA_WR08(chip->PCIO, 0x03D5, 0); in LoadStateExt()
1658 VGA_WR08(chip->PCIO, 0x03D4, 0x21); in LoadStateExt()
1659 VGA_WR08(chip->PCIO, 0x03D5, 0xfa); in LoadStateExt()
1662 VGA_WR08(chip->PCIO, 0x03D4, 0x41); in LoadStateExt()
1663 VGA_WR08(chip->PCIO, 0x03D5, state->extra); in LoadStateExt()
1670 VGA_WR08(chip->PCIO, 0x03D4, 0x19); in LoadStateExt()
1671 VGA_WR08(chip->PCIO, 0x03D5, state->repaint0); in LoadStateExt()
1672 VGA_WR08(chip->PCIO, 0x03D4, 0x1A); in LoadStateExt()
1673 VGA_WR08(chip->PCIO, 0x03D5, state->repaint1); in LoadStateExt()
1674 VGA_WR08(chip->PCIO, 0x03D4, 0x25); in LoadStateExt()
1675 VGA_WR08(chip->PCIO, 0x03D5, state->screen); in LoadStateExt()
1676 VGA_WR08(chip->PCIO, 0x03D4, 0x28); in LoadStateExt()
1677 VGA_WR08(chip->PCIO, 0x03D5, state->pixel); in LoadStateExt()
1678 VGA_WR08(chip->PCIO, 0x03D4, 0x2D); in LoadStateExt()
1679 VGA_WR08(chip->PCIO, 0x03D5, state->horiz); in LoadStateExt()
1680 VGA_WR08(chip->PCIO, 0x03D4, 0x1B); in LoadStateExt()
1681 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration0); in LoadStateExt()
1682 VGA_WR08(chip->PCIO, 0x03D4, 0x20); in LoadStateExt()
1683 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration1); in LoadStateExt()
1684 VGA_WR08(chip->PCIO, 0x03D4, 0x30); in LoadStateExt()
1685 VGA_WR08(chip->PCIO, 0x03D5, state->cursor0); in LoadStateExt()
1686 VGA_WR08(chip->PCIO, 0x03D4, 0x31); in LoadStateExt()
1687 VGA_WR08(chip->PCIO, 0x03D5, state->cursor1); in LoadStateExt()
1688 VGA_WR08(chip->PCIO, 0x03D4, 0x2F); in LoadStateExt()
1689 VGA_WR08(chip->PCIO, 0x03D5, state->cursor2); in LoadStateExt()
1690 VGA_WR08(chip->PCIO, 0x03D4, 0x39); in LoadStateExt()
1691 VGA_WR08(chip->PCIO, 0x03D5, state->interlace); in LoadStateExt()
1694 NV_WR32(chip->PRAMDAC0, 0x00000508, state->vpll); in LoadStateExt()
1695 NV_WR32(chip->PRAMDAC0, 0x0000050C, state->pllsel); in LoadStateExt()
1697 NV_WR32(chip->PRAMDAC0, 0x00000520, state->vpll2); in LoadStateExt()
1699 NV_WR32(chip->PRAMDAC, 0x00000848 , state->scale); in LoadStateExt()
1701 NV_WR32(chip->PRAMDAC, 0x00000600 , state->general); in LoadStateExt()
1706 NV_WR32(chip->PCRTC, 0x00000140, 0); in LoadStateExt()
1707 NV_WR32(chip->PCRTC, 0x00000100, chip->VBlankBit); in LoadStateExt()
1711 NV_WR32(chip->PMC, 0x00000140, chip->EnableIRQ & 0x01); in LoadStateExt()
1719 chip->FifoFreeCount = 0; in LoadStateExt()
1721 chip->FifoEmptyCount = NV_RD32(&chip->Rop->FifoFree, 0); in LoadStateExt()
1732 VGA_WR08(chip->PCIO, 0x03D4, 0x19); in UnloadStateExt()
1733 state->repaint0 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1734 VGA_WR08(chip->PCIO, 0x03D4, 0x1A); in UnloadStateExt()
1735 state->repaint1 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1736 VGA_WR08(chip->PCIO, 0x03D4, 0x25); in UnloadStateExt()
1737 state->screen = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1738 VGA_WR08(chip->PCIO, 0x03D4, 0x28); in UnloadStateExt()
1739 state->pixel = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1740 VGA_WR08(chip->PCIO, 0x03D4, 0x2D); in UnloadStateExt()
1741 state->horiz = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1742 VGA_WR08(chip->PCIO, 0x03D4, 0x1B); in UnloadStateExt()
1743 state->arbitration0 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1744 VGA_WR08(chip->PCIO, 0x03D4, 0x20); in UnloadStateExt()
1745 state->arbitration1 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1746 VGA_WR08(chip->PCIO, 0x03D4, 0x30); in UnloadStateExt()
1747 state->cursor0 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1748 VGA_WR08(chip->PCIO, 0x03D4, 0x31); in UnloadStateExt()
1749 state->cursor1 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1750 VGA_WR08(chip->PCIO, 0x03D4, 0x2F); in UnloadStateExt()
1751 state->cursor2 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1752 VGA_WR08(chip->PCIO, 0x03D4, 0x39); in UnloadStateExt()
1753 state->interlace = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1754 state->vpll = NV_RD32(chip->PRAMDAC0, 0x00000508); in UnloadStateExt()
1755 state->vpll2 = NV_RD32(chip->PRAMDAC0, 0x00000520); in UnloadStateExt()
1756 state->pllsel = NV_RD32(chip->PRAMDAC0, 0x0000050C); in UnloadStateExt()
1757 state->general = NV_RD32(chip->PRAMDAC, 0x00000600); in UnloadStateExt()
1758 state->scale = NV_RD32(chip->PRAMDAC, 0x00000848); in UnloadStateExt()
1759 state->config = NV_RD32(chip->PFB, 0x00000200); in UnloadStateExt()
1763 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000630); in UnloadStateExt()
1764 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000634); in UnloadStateExt()
1765 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000638); in UnloadStateExt()
1766 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000063C); in UnloadStateExt()
1767 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000650); in UnloadStateExt()
1768 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000654); in UnloadStateExt()
1769 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000658); in UnloadStateExt()
1770 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000065C); in UnloadStateExt()
1773 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640); in UnloadStateExt()
1774 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644); in UnloadStateExt()
1775 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648); in UnloadStateExt()
1776 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C); in UnloadStateExt()
1777 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670); in UnloadStateExt()
1778 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674); in UnloadStateExt()
1779 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678); in UnloadStateExt()
1780 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C); in UnloadStateExt()
1785 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640); in UnloadStateExt()
1786 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644); in UnloadStateExt()
1787 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648); in UnloadStateExt()
1788 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C); in UnloadStateExt()
1789 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670); in UnloadStateExt()
1790 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674); in UnloadStateExt()
1791 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678); in UnloadStateExt()
1792 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C); in UnloadStateExt()
1794 state->head = NV_RD32(chip->PCRTC0, 0x00000860); in UnloadStateExt()
1795 state->head2 = NV_RD32(chip->PCRTC0, 0x00002860); in UnloadStateExt()
1796 VGA_WR08(chip->PCIO, 0x03D4, 0x44); in UnloadStateExt()
1797 state->crtcOwner = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1799 VGA_WR08(chip->PCIO, 0x03D4, 0x41); in UnloadStateExt()
1800 state->extra = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1801 state->cursorConfig = NV_RD32(chip->PCRTC, 0x00000810); in UnloadStateExt()
1803 if((chip->Chipset & 0x0ff0) == 0x0110) { in UnloadStateExt()
1804 state->dither = NV_RD32(chip->PRAMDAC, 0x0528); in UnloadStateExt()
1806 if((chip->Chipset & 0x0ff0) >= 0x0170) { in UnloadStateExt()
1807 state->dither = NV_RD32(chip->PRAMDAC, 0x083C); in UnloadStateExt()
1818 NV_WR32(chip->PCRTC, 0x800, start); in SetStartAddress()
1834 chip->LockUnlock(chip, 0); in SetStartAddress3()
1838 VGA_WR08(chip->PCIO, 0x3D4, 0x0D); VGA_WR08(chip->PCIO, 0x3D5, offset); in SetStartAddress3()
1840 VGA_WR08(chip->PCIO, 0x3D4, 0x0C); VGA_WR08(chip->PCIO, 0x3D5, offset); in SetStartAddress3()
1842 VGA_WR08(chip->PCIO, 0x3D4, 0x19); tmp = VGA_RD08(chip->PCIO, 0x3D5); in SetStartAddress3()
1843 VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x01F) | (tmp & ~0x1F)); in SetStartAddress3()
1844 VGA_WR08(chip->PCIO, 0x3D4, 0x2D); tmp = VGA_RD08(chip->PCIO, 0x3D5); in SetStartAddress3()
1845 VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x60) | (tmp & ~0x60)); in SetStartAddress3()
1849 offset = VGA_RD08(chip->PCIO, chip->IO + 0x0A); in SetStartAddress3()
1850 VGA_WR08(chip->PCIO, 0x3C0, 0x13); in SetStartAddress3()
1851 VGA_WR08(chip->PCIO, 0x3C0, pan); in SetStartAddress3()
1861 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); in nv3SetSurfaces2D()
1864 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003); in nv3SetSurfaces2D()
1865 NV_WR32(&Surface->Offset, 0, surf0); in nv3SetSurfaces2D()
1866 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004); in nv3SetSurfaces2D()
1867 NV_WR32(&Surface->Offset, 0, surf1); in nv3SetSurfaces2D()
1868 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013); in nv3SetSurfaces2D()
1878 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); in nv4SetSurfaces2D()
1880 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003); in nv4SetSurfaces2D()
1881 NV_WR32(&Surface->Offset, 0, surf0); in nv4SetSurfaces2D()
1882 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004); in nv4SetSurfaces2D()
1883 NV_WR32(&Surface->Offset, 0, surf1); in nv4SetSurfaces2D()
1884 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); in nv4SetSurfaces2D()
1894 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); in nv10SetSurfaces2D()
1896 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003); in nv10SetSurfaces2D()
1897 NV_WR32(&Surface->Offset, 0, surf0); in nv10SetSurfaces2D()
1898 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004); in nv10SetSurfaces2D()
1899 NV_WR32(&Surface->Offset, 0, surf1); in nv10SetSurfaces2D()
1900 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); in nv10SetSurfaces2D()
1910 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); in nv3SetSurfaces3D()
1913 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005); in nv3SetSurfaces3D()
1914 NV_WR32(&Surface->Offset, 0, surf0); in nv3SetSurfaces3D()
1915 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006); in nv3SetSurfaces3D()
1916 NV_WR32(&Surface->Offset, 0, surf1); in nv3SetSurfaces3D()
1917 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013); in nv3SetSurfaces3D()
1927 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); in nv4SetSurfaces3D()
1929 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005); in nv4SetSurfaces3D()
1930 NV_WR32(&Surface->Offset, 0, surf0); in nv4SetSurfaces3D()
1931 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006); in nv4SetSurfaces3D()
1932 NV_WR32(&Surface->Offset, 0, surf1); in nv4SetSurfaces3D()
1933 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); in nv4SetSurfaces3D()
1943 (RivaSurface3D __iomem *)&(chip->FIFO[0x0000E000/4]); in nv10SetSurfaces3D()
1946 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000007); in nv10SetSurfaces3D()
1947 NV_WR32(&Surfaces3D->RenderBufferOffset, 0, surf0); in nv10SetSurfaces3D()
1948 NV_WR32(&Surfaces3D->ZBufferOffset, 0, surf1); in nv10SetSurfaces3D()
1949 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); in nv10SetSurfaces3D()
1966 if (NV_RD32(&chip->PFB[0x00000000/4], 0) & 0x00000020) in nv3GetConfig()
1968 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20) in nv3GetConfig()
1969 && ((NV_RD32(chip->PMC, 0x00000000) & 0x0F) >= 0x02)) in nv3GetConfig()
1975 switch (NV_RD32(chip->PFB, 0x00000000) & 0x03) in nv3GetConfig()
2000 switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) in nv3GetConfig()
2002 case 0: in nv3GetConfig()
2013 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500; in nv3GetConfig()
2014 chip->CURSOR = &(chip->PRAMIN[0x00008000/4 - 0x0800/4]); in nv3GetConfig()
2015 chip->VBlankBit = 0x00000100; in nv3GetConfig()
2037 if (NV_RD32(chip->PFB, 0x00000000) & 0x00000100) in nv4GetConfig()
2039 chip->RamAmountKBytes = ((NV_RD32(chip->PFB, 0x00000000) >> 12) & 0x0F) * 1024 * 2 in nv4GetConfig()
2044 switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) in nv4GetConfig()
2046 case 0: in nv4GetConfig()
2061 switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003) in nv4GetConfig()
2070 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500; in nv4GetConfig()
2071 chip->CURSOR = &(chip->PRAMIN[0x00010000/4 - 0x0800/4]); in nv4GetConfig()
2072 chip->VBlankBit = 0x00000001; in nv4GetConfig()
2099 if(!(NV_RD32(chip->PMC, 0x00000004) & 0x01000001)) in nv10GetConfig()
2100 NV_WR32(chip->PMC, 0x00000004, 0x01000001); in nv10GetConfig()
2107 dev = pci_get_domain_bus_and_slot(domain, 0, 1); in nv10GetConfig()
2108 pci_read_config_dword(dev, 0x7C, &amt); in nv10GetConfig()
2112 dev = pci_get_domain_bus_and_slot(domain, 0, 1); in nv10GetConfig()
2113 pci_read_config_dword(dev, 0x84, &amt); in nv10GetConfig()
2117 switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) & 0x000000FF) in nv10GetConfig()
2119 case 0x02: in nv10GetConfig()
2122 case 0x04: in nv10GetConfig()
2125 case 0x08: in nv10GetConfig()
2128 case 0x10: in nv10GetConfig()
2131 case 0x20: in nv10GetConfig()
2134 case 0x40: in nv10GetConfig()
2137 case 0x80: in nv10GetConfig()
2145 switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003) in nv10GetConfig()
2154 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 6)) ? in nv10GetConfig()
2157 switch (chipset & 0x0ff0) { in nv10GetConfig()
2158 case 0x0170: in nv10GetConfig()
2159 case 0x0180: in nv10GetConfig()
2160 case 0x01F0: in nv10GetConfig()
2161 case 0x0250: in nv10GetConfig()
2162 case 0x0280: in nv10GetConfig()
2163 case 0x0300: in nv10GetConfig()
2164 case 0x0310: in nv10GetConfig()
2165 case 0x0320: in nv10GetConfig()
2166 case 0x0330: in nv10GetConfig()
2167 case 0x0340: in nv10GetConfig()
2168 if(NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 22)) in nv10GetConfig()
2177 chip->VBlankBit = 0x00000001; in nv10GetConfig()
2191 switch(chipset & 0x0ff0) { in nv10GetConfig()
2192 case 0x0110: in nv10GetConfig()
2193 case 0x0170: in nv10GetConfig()
2194 case 0x0180: in nv10GetConfig()
2195 case 0x01F0: in nv10GetConfig()
2196 case 0x0250: in nv10GetConfig()
2197 case 0x0280: in nv10GetConfig()
2198 case 0x0300: in nv10GetConfig()
2199 case 0x0310: in nv10GetConfig()
2200 case 0x0320: in nv10GetConfig()
2201 case 0x0330: in nv10GetConfig()
2202 case 0x0340: in nv10GetConfig()
2244 chip->Rop = (RivaRop __iomem *)&(chip->FIFO[0x00000000/4]); in RivaGetConfig()
2245 chip->Clip = (RivaClip __iomem *)&(chip->FIFO[0x00002000/4]); in RivaGetConfig()
2246 chip->Patt = (RivaPattern __iomem *)&(chip->FIFO[0x00004000/4]); in RivaGetConfig()
2247 chip->Pixmap = (RivaPixmap __iomem *)&(chip->FIFO[0x00006000/4]); in RivaGetConfig()
2248 chip->Blt = (RivaScreenBlt __iomem *)&(chip->FIFO[0x00008000/4]); in RivaGetConfig()
2249 chip->Bitmap = (RivaBitmap __iomem *)&(chip->FIFO[0x0000A000/4]); in RivaGetConfig()
2250 chip->Line = (RivaLine __iomem *)&(chip->FIFO[0x0000C000/4]); in RivaGetConfig()
2251 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); in RivaGetConfig()
2252 return (0); in RivaGetConfig()