119 	struct lcd_ctrl_extif	*extif;  member
131 	hwa742.extif->set_bits_per_cycle(8);  in hwa742_read_reg()
132 	hwa742.extif->write_command(&reg, 1);  in hwa742_read_reg()
133 	hwa742.extif->read_data(&data, 1);  in hwa742_read_reg()
140 	hwa742.extif->set_bits_per_cycle(8);  in hwa742_write_reg()
141 	hwa742.extif->write_command(&reg, 1);  in hwa742_write_reg()
142 	hwa742.extif->write_data(&data, 1);  in hwa742_write_reg()
161 	hwa742.extif->set_bits_per_cycle(8);  in set_window_regs()
164 	hwa742.extif->write_command(&cmd, 1);  in set_window_regs()
166 	hwa742.extif->write_data(tmp, 8);  in set_window_regs()
198 		hwa742.extif->enable_tearsync(1, 0);  in enable_tearsync()
203 		hwa742.extif->enable_tearsync(1, 0);  in enable_tearsync()
209 		hwa742.extif->enable_tearsync(1, 0);  in enable_tearsync()
213 	hwa742.extif->enable_tearsync(1, y + 1);  in enable_tearsync()
220 	hwa742.extif->enable_tearsync(0, 0);  in disable_tearsync()
389 	hwa742.extif->set_bits_per_cycle(16);  in send_frame_handler()
392 	hwa742.extif->transfer_area(w, h, request_complete, req);  in send_frame_handler()
665 	return hwa742.extif->convert_timings(t);  in calc_reg_timing()
716 	return hwa742.extif->convert_timings(t);  in calc_lut_timing()
724 	hwa742.extif->get_clk_info(&hwa742.extif_clk_period, &max_clk_div);  in calc_extif_timings()
801 	if (hwa742.extif->get_max_tx_rate != NULL) {  in setup_tearsync()
807 		unsigned long max_tx_rate = hwa742.extif->get_max_tx_rate();  in setup_tearsync()
881 	return hwa742.extif->setup_tearsync(1, hs, vs,  in setup_tearsync()
934 	hwa742.extif = fbdev->ext_if;  in hwa742_init()
946 	if ((r = hwa742.extif->init(fbdev)) < 0)  in hwa742_init()
952 	hwa742.extif->set_timings(&hwa742.reg_timings);  in hwa742_init()
958 	hwa742.extif->set_timings(&hwa742.reg_timings);  in hwa742_init()
982 	hwa742.max_transmit_size = hwa742.extif->max_transmit_size;  in hwa742_init()
1014 	hwa742.extif->cleanup();  in hwa742_init()
1024 	hwa742.extif->cleanup();  in hwa742_cleanup()