169 	TVPADDRW = 0x00,	/* 0  Palette/Cursor RAM Write Address/Index */  enumerator
620 	par->cmap_regs[TVPADDRW] = TVPIRPLA;		eieio();  in set_imstt_regvals_tvp()
622 	par->cmap_regs[TVPADDRW] = TVPIRPPD;		eieio();  in set_imstt_regvals_tvp()
624 	par->cmap_regs[TVPADDRW] = TVPIRPPD;		eieio();  in set_imstt_regvals_tvp()
626 	par->cmap_regs[TVPADDRW] = TVPIRPPD;		eieio();  in set_imstt_regvals_tvp()
629 	par->cmap_regs[TVPADDRW] = TVPIRTCC;		eieio();  in set_imstt_regvals_tvp()
631 	par->cmap_regs[TVPADDRW] = TVPIRMXC;		eieio();  in set_imstt_regvals_tvp()
633 	par->cmap_regs[TVPADDRW] = TVPIRMIC;		eieio();  in set_imstt_regvals_tvp()
636 	par->cmap_regs[TVPADDRW] = TVPIRPLA;		eieio();  in set_imstt_regvals_tvp()
638 	par->cmap_regs[TVPADDRW] = TVPIRLPD;		eieio();  in set_imstt_regvals_tvp()
641 	par->cmap_regs[TVPADDRW] = TVPIRPLA;		eieio();  in set_imstt_regvals_tvp()
643 	par->cmap_regs[TVPADDRW] = TVPIRMLC;		eieio();  in set_imstt_regvals_tvp()
646 	par->cmap_regs[TVPADDRW] = TVPIRPLA;		eieio();  in set_imstt_regvals_tvp()
648 	par->cmap_regs[TVPADDRW] = TVPIRLPD;		eieio();  in set_imstt_regvals_tvp()
761 		par->cmap_regs[TVPADDRW] = TVPIRTCC;	eieio();  in set_555()
774 		par->cmap_regs[TVPADDRW] = TVPIRTCC;	eieio();  in set_565()
1126 		par->cmap_regs[TVPADDRW] = TVPIRICC;	eieio();
1128 		par->cmap_regs[TVPADDRW] = 0;		eieio();
1135 		par->cmap_regs[TVPADDRW] = TVPIRICC;	eieio();
1139 				par->cmap_regs[TVPADDRW] = x + y * 8;	eieio();
1142 		par->cmap_regs[TVPADDRW] = TVPIRICC;	eieio();
1146 				par->cmap_regs[TVPADDRW] = x + y * 8;	eieio();
1180 			par->cmap_regs[TVPADDRW] = TVPIRICC;	eieio();
1189 			par->cmap_regs[TVPADDRW] = TVPIRICC;	eieio();
1384 			par->cmap_regs[TVPADDRW] = tvp_initregs[i].addr;  in init_imstt()