26 	int ret;  in ssusb_check_clocks()  local
31 	ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS1, value,  in ssusb_check_clocks()
33 	if (ret) {  in ssusb_check_clocks()
35 		return ret;  in ssusb_check_clocks()
38 	ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS2, value,  in ssusb_check_clocks()
40 	if (ret) {  in ssusb_check_clocks()
42 		return ret;  in ssusb_check_clocks()
51 	int ret;  in ssusb_phy_init()  local
54 		ret = phy_init(ssusb->phys[i]);  in ssusb_phy_init()
55 		if (ret)  in ssusb_phy_init()
64 	return ret;  in ssusb_phy_init()
80 	int ret;  in ssusb_phy_power_on()  local
83 		ret = phy_power_on(ssusb->phys[i]);  in ssusb_phy_power_on()
84 		if (ret)  in ssusb_phy_power_on()
93 	return ret;  in ssusb_phy_power_on()
106 	int ret;  in ssusb_clks_enable()  local
108 	ret = clk_prepare_enable(ssusb->sys_clk);  in ssusb_clks_enable()
109 	if (ret) {  in ssusb_clks_enable()
114 	ret = clk_prepare_enable(ssusb->ref_clk);  in ssusb_clks_enable()
115 	if (ret) {  in ssusb_clks_enable()
120 	ret = clk_prepare_enable(ssusb->mcu_clk);  in ssusb_clks_enable()
121 	if (ret) {  in ssusb_clks_enable()
126 	ret = clk_prepare_enable(ssusb->dma_clk);  in ssusb_clks_enable()
127 	if (ret) {  in ssusb_clks_enable()
141 	return ret;  in ssusb_clks_enable()
154 	int ret = 0;  in ssusb_rscs_init()  local
156 	ret = regulator_enable(ssusb->vusb33);  in ssusb_rscs_init()
157 	if (ret) {  in ssusb_rscs_init()
162 	ret = ssusb_clks_enable(ssusb);  in ssusb_rscs_init()
163 	if (ret)  in ssusb_rscs_init()
166 	ret = ssusb_phy_init(ssusb);  in ssusb_rscs_init()
167 	if (ret) {  in ssusb_rscs_init()
172 	ret = ssusb_phy_power_on(ssusb);  in ssusb_rscs_init()
173 	if (ret) {  in ssusb_rscs_init()
187 	return ret;  in ssusb_rscs_init()
220 	int ret;  in get_ssusb_rscs()  local
277 	ret = ssusb_wakeup_of_property_parse(ssusb, node);  in get_ssusb_rscs()
278 	if (ret) {  in get_ssusb_rscs()
280 		return ret;  in get_ssusb_rscs()
323 	int ret = -ENOMEM;  in mtu3_probe()  local
330 	ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));  in mtu3_probe()
331 	if (ret) {  in mtu3_probe()
339 	ret = get_ssusb_rscs(pdev, ssusb);  in mtu3_probe()
340 	if (ret)  in mtu3_probe()
341 		return ret;  in mtu3_probe()
350 	ret = ssusb_rscs_init(ssusb);  in mtu3_probe()
351 	if (ret)  in mtu3_probe()
366 		ret = ssusb_gadget_init(ssusb);  in mtu3_probe()
367 		if (ret) {  in mtu3_probe()
373 		ret = ssusb_host_init(ssusb, node);  in mtu3_probe()
374 		if (ret) {  in mtu3_probe()
380 		ret = ssusb_gadget_init(ssusb);  in mtu3_probe()
381 		if (ret) {  in mtu3_probe()
386 		ret = ssusb_host_init(ssusb, node);  in mtu3_probe()
387 		if (ret) {  in mtu3_probe()
392 		ret = ssusb_otg_switch_init(ssusb);  in mtu3_probe()
393 		if (ret) {  in mtu3_probe()
400 		ret = -EINVAL;  in mtu3_probe()
417 	return ret;  in mtu3_probe()
473 	int ret;  in mtu3_resume()  local
481 	ret = ssusb_clks_enable(ssusb);  in mtu3_resume()
482 	if (ret)  in mtu3_resume()
485 	ret = ssusb_phy_power_on(ssusb);  in mtu3_resume()
486 	if (ret)  in mtu3_resume()
496 	return ret;  in mtu3_resume()